Physical Design Engineer

Terranova Talent Solutions; San Jose (CA); On-site; USD 150,000 - 230,000; Full time

Benefits offered by this job

Relocation assistance

Job summary

Terranova Talent Solutions is seeking an experienced ASIC/SoC Physical Design Engineer in San Jose, CA. You will execute RTL synthesis using Cadence Genus and develop floorplans with Innovus, while optimizing PPA and collaborating with RTL and architecture teams to ensure robust timing and design quality.

The role requires 5+ years in physical design, familiarity with advanced nodes (5nm/3nm+), and strong communication across distributed teams.

Qualifications

• Must hold a Bachelor's degree in Electrical/Computer Engineering or related field.
• 5+ years of ASIC/SoC Physical Design experience.
• Hands-on with synthesis and floorplanning tools.
• Strong knowledge of timing, synthesis, physical implementation and PPA optimization.
• Experience with advanced process nodes (5nm, 3nm or newer).
• Excellent communication and cross-team collaboration skills.

Responsibilities

• Execute RTL synthesis for ASIC/SoC designs using Cadence Genus.
• Optimize designs for power, performance, and area (PPA) across flow.
• Develop and optimize floorplans using Cadence Innovus.
• Collaborate with RTL, architecture, and design teams on timing and constraints.
• Partner with physical implementation teams to achieve timing closure and quality goals.
• Analyze timing challenges, identify critical paths, and suggest improvements.
• Support physical implementation from synthesis to final design while meeting schedule objectives.

Job description

• Execute RTL synthesis for complex ASIC and SoC designs using Cadence Genus.
• Optimize designs for power, performance, and area (PPA) throughout the synthesis and physical design flow.
• Develop and improve floorplans using Cadence Innovus, ensuring efficient utilization and routing.
• Collaborate with RTL, architecture, and design teams to provide feedback on timing, constraints, and implementation strategies.
• Partner with physical implementation and place-and-route teams to achieve timing closure and design quality goals.
• Analyze timing challenges, identify critical paths, and recommend design improvements to improve convergence.
• Support physical implementation activities from synthesis through implementation while maintaining design quality and schedule objectives.

Required Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related discipline.
• 5+ years of experience in ASIC or SoC Physical Design.
• Hands-on expertise with Cadence Genus for synthesis and Cadence Innovus for floorplanning and implementation.
• Experience working on large, high-performance semiconductor designs with demanding timing requirements.
• Strong knowledge of synthesis, timing analysis, physical implementation, and PPA optimization.
• Experience with advanced semiconductor process technologies such as 5nm, 3nm, or newer.
• Excellent communication skills and the ability to work effectively with RTL, architecture, physical design, and implementation teams.
• Preferred Qualifications
• Experience supporting complex SoC, AI, HPC, or accelerator designs.
• Strong understanding of timing closure methodologies and synthesis-to-implementation correlation.
• Familiarity with advanced implementation flows, design constraints, and physical optimization techniques.
• Proven ability to collaborate with globally distributed engineering teams to deliver successful silicon implementations.