Senior Physical Design Engineer

Value Innovation Labs; Sunnyvale (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

Value Innovation Labs is seeking a Senior Physical Design Engineer to lead RTL-to-GDSII implementation for low-power SoCs on advanced nodes. You will drive the full physical design flow from synthesis to GDSII, including floorplanning, placement, CTS, routing and timing closure.

You will handle SDC constraints and UPF promotion, develop automation flows with Tcl, Python and Shell, and mentor junior engineers while collaborating on design closure and signoff across the SoC hierarchy.

Qualifications

• Experience in RTL-to-GDSII flow for low-power SoCs.
• Hands-on with floorplanning, CTS, routing, and timing closure.
• Strong scripting skills in Tcl, Python, and Shell.
• Experience with SDC and UPF constraint/promotion.
• Ability to develop automation flows and methodologies.
• Collaborate on design closure and signoff.

Responsibilities

• Drive physical design flow from synthesis to GDSII
• Floorplanning, placement, CTS, routing, and timing closure
• Handle SDC constraints and UPF promotion/pushdown
• Develop automation flows using Tcl, Python, and Shell
• Collaborate on design closure and signoff
• Mentor junior team members
• Contribute to flow and methodology improvements
• SoC hierarchy and integration
• Signoff flows and constraint management

Skills

RTL-to-GDSII implementation

Physical design flow

Floorplanning

Placement & routing

Timing closure

SDC constraints

UPF promotion/pushdown

Tcl scripting

Python scripting

Mentoring

Education

B.Tech/M.Tech in ECE/EE/VLSI

Job description

We are looking for a Senior Physical Design Engineer with strong experience in RTL-to-GDSII implementation for low-power SoCs on advanced nodes.

• Drive physical design flow from synthesis to GDSII
• Floorplanning, placement, CTS, routing, and timing closure
• Handle SDC constraints and UPF promotion/pushdown
• Develop automation flows using Tcl, Python, and Shell
• Collaborate on design closure and signoff
• Mentor junior team members
• Contribute to flow and methodology improvements
• SoC hierarchy and integration
• Signoff flows and constraint management

Education:

B.Tech/M.Tech in ECE, EE, VLSI or related field