Physical Design Lead

Quest Global; San Jose (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

Quest Global in San Jose is seeking a seasoned Physical Design Expert to lead a silicon implementation team, driving RTL-to-GDS flow, sign-off, and full-chip integration. You will collaborate with SOC architects, PD/STA engineers and IP teams to ensure first-pass silicon success.

Your role emphasizes backend convergence, PnR, timing, verification and IP integration, with responsibility for delivering tape-outs from RTL to GDS.

Qualifications

• 15+ years in physical design RTL to GDS, STA, timing and tapeout.
• Block-level implementation incl. Place & Route, floorplanning, timing closure.
• Experience with PD verification signoff techniques and EDA tools.

Responsibilities

• Lead physical design team for implementation and convergence of complex tiles.
• Deliver GDS from RTL including signoff and physical verification.
• Collaborate with cross-functional teams to improve PPA.
• Understand and drive timing convergence, full-chip integration and IP integration.
• Track milestones and project convergence; communicate status clearly.
• Drive methodology development and best practices in PD.
• Provide technical direction and support to the engineering team.

Skills

Physical design

RTL to GDS

PPA optimization

Scripting (Perl/TCL/Shell/Python)

Verilog/VHDL RTL design

Communication skills

Education

B.Tech/M.Tech/MS/Ph.D. in Computer/Electronics/Electrical Engineering

Tools

Cadence Innovus

Job description

As a member of the Quest Global Physical Design team, you will help bring to life cutting-edge designs. As a member and lead of the Physical design team, you will work closely with the SOC architects, Physical design architects, design leads, IP teams, Physical Design leads and PD/STA engineers to achieve first-pass silicon success. You will be expected to lead design implementation and convergence activities in the backend from a PnR implementation perspective.

In this position as a Physical Design Expert, you will be part of a world-class team developing groundbreaking high-performance IP, Test chip and Chiplet designs . This is a great opportunity to join a talented team that is well-invested in the implementation of futuristic designs in advanced process nodes.

You will be responsible for driving a team of silicon design engineers for the successful delivery of project tape-outs from RTL-GDS.

You will use your knowledge of Physical design to lead a complete set of Backend activities, Specifically PnR, timing, verification and signoff including IP integration and full-chip aspects.

This position requires a detail-oriented candidate, who possesses good communication skills and can handle/work with teams.

Key Responsibilities

• Lead Physical design team for implementation and convergence of highly complex tiles
• Will be responsible for delivery of GDS starting from RTL including Signoff and physical verification.
• Collaborate with cross-functional teams to drive continuous improvements for achieving better PPA.
• Good understanding of horizontal sign-off flows like VCLP, Formal Equivalence, Low Power Checks, timing convergence (both tile-level and FCT), and full chip integration flows.
• Understanding design requirements, timelines and various milestones of a project and tracking project convergence status accordingly covering all aspects of the design cycle.
• Drive methodology development ideas/forums.
• Provide technical direction, guidance, and Support to the engineering team.

Preferred Experience

• Experienced PD professional with a minimum of 15 years of industry experience in the Physical design domain (RTL to GDS, STA, Physical verification, timing signoff, tapeout).
• Block-level implementation (Place and Route), which includes Floorplanning, Timing Closure and Physical Verification.
• Well-versed with Physical Design verification signoff techniques such as Formal equivalence, IR&EM, Timing Closure (STA), Physical verification, VSI, Formal Equivalence Check or LEC, etc.
• Good understanding of Power, Performance and Area (PPA) optimization techniques.
• Good experience with Perl/TCL/Shell/Python scripting, and Verilog/VHDL RTL design.
• Excellent presentation and inter-communication skills.

Qualifications

• B.Tech/M.Tech/MS/Ph.D. in Computer/Electronics/Electrical Engineering.
• Candidate must have the ability to drive/manage projects from RTL to GDS, with a minimum experience of managing more than 4 tape-outs.
• Proficient in physical design industry-standard EDA tools Cadence Innovus