Physical Design Engineer II: ASIC/SoC Innovation

Microchip Technology Inc.; Chandler (AZ); Sur place; USD 100 000 - 150 000; Plein temps

Résumé du poste

Microchip Technology Inc. is seeking an Engineer II-Physical Design to join our Physical Design team in Chandler, AZ.

You will work on ASIC/SoC physical design, synthesis, floorplanning, placement, clocking, routing, timing, power, physical verification, and tapeout-readiness with 2.5–5 years of relevant experience. You will collaborate with architecture, RTL design, verification, DFT, analog, package, methodology, CAD, product, test, and manufacturing teams to ensure robust performance, power,

Qualifications

• Bachelor’s degree and 2.5–5 years in ASIC/SoC physical design or closely related area.
• Experience in synthesis, floorplanning, place-and-route, and timing closure.
• Familiarity with EDA flows, power integrity, and physical verification.

Responsabilités

• Develop ASIC/SoC physical‑design blocks, constraints, scripts, flows, and design data.
• Translate architecture and RTL to synthesis, floorplan, placement, clocking, routing, timing, power, verification.
• Execute implementation, timing, power, and signoff checks; troubleshoot issues.
• Coordinate deliverables across architecture, RTL design, verification, DFT, analog, package, methodology, CAD, product, test, and manufacturing teams.
• Support automation and continuous improvement.

Connaissances

ASIC/SoC physical design

Synthesis

Floorplanning

Place & Route

Timing closure

Power integrity

Physical verification

Scripting

Cross-functional collaboration

Formation

Bachelor's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, Computer Science, Physics, or a related field

Outils

EDA tools

Description du poste

Microchip Technology Inc. is seeking an Engineer II-Physical Design to join our Physical Design team in Chandler, AZ.

You will work on ASIC/SoC physical design, synthesis, floorplanning, placement, clocking, routing, timing, power, physical verification, and tapeout-readiness with 2.5–5 years of relevant experience. You will collaborate with architecture, RTL design, verification, DFT, analog, package, methodology, CAD, product, test, and manufacturing teams to ensure robust performance, power,