Principal Engineer, Full-Chip Physical Design

FHLB Des Moines; Chandler, Northern (AZ, KY); Hybrid; USD 140,000 - 190,000; Full time

Job summary

Microchip Technology Inc is seeking a Principal Engineer to own full-chip APR and physical implementation, including netlist-to-GDSII, for advanced designs in Chandler, AZ. This role demands 10+ years of hands-on physical design experience across floorplanning, placement, clock-tree synthesis, routing, and sign-off.

You will lead cross-functional activities with a worldwide PD team, using ICC/ICC2 or Innovus and UPF low-power practices.

Qualifications

• Bachelor’s or Masters Degree in Electrical / Electronics Engineering with 10+ years of relevant experience.
• Hands-on experience in physical design flows such as floor planning, placement optimization.
• Clock tree synthesis, routing, crosstalk avoidance and physical verification experience.
• Advanced knowledge of place and route methodologies and timing closure.
• Experience with full chip Physical Design activities and sign-off tools.
• Knowledge of UPF and Low Power design practices throughout the flow.
• Proficiency in Tcl and Perl scripting.
• Excellent communication and problem-solving skills.
• Self-motivated team player with collaboration across globally distributed teams.

Responsibilities

• Lead full Chip APR and Physical Implementation (Netlist-to-GDSII).
• Collaborate with global teams across design groups to meet goals.
• Develop and optimize floorplanning, placement, and routing strategies.
• Ensure timing closure and design sign-off across multiple tech nodes.
• Mentor engineers and improve PD flows and methodologies.

Skills

Floor planning

Placement optimization

Clock tree synthesis

Routing

Crosstalk avoidance

Physical verification

VLSI timing closure

Tcl scripting

Perl scripting

Team collaboration

Problem solving

Education

Electrical/Electronics Engineering degree (Bachelor or Master)

Tools

ICC/ICC2

Innovus

Parasitic Extraction

Sign-off tools

Job description

Microchip Technology Inc is seeking a Principal Engineer to own full-chip APR and physical implementation, including netlist-to-GDSII, for advanced designs in Chandler, AZ. This role demands 10+ years of hands-on physical design experience across floorplanning, placement, clock-tree synthesis, routing, and sign-off.

You will lead cross-functional activities with a worldwide PD team, using ICC/ICC2 or Innovus and UPF low-power practices.