Engineer II - Physical Design

Microchip Technology; Chandler (AZ); Presencial; USD 90.000 - 140.000; Jornada completa

Descripción de la vacante

Microchip Technology Inc. in Chandler, AZ is seeking an Engineer II-Physical Design to contribute to ASIC/SoC layout, floorplanning, timing, and tapeout-readiness.

You will work with architecture, RTL, verification, DFT, CAD, and manufacturing teams to deliver robust performance, power, and area.

Candidates with 2.5–5 years in PD and a Bachelor's degree are encouraged to apply; on-site role with growth opportunities.

Formación

• Bachelor's degree in Electrical Engineering, Electronics Engineering, or Computer Engineering.
• 2.5–5 years of ASIC/SoC physical design experience including synthesis, floorplanning, placement, and timing closure.
• Strong analytical, problem-solving, and cross-functional collaboration skills.

Responsabilidades

• Develop and maintain ASIC/SoC physical-design blocks, constraints, scripts, and flows.
• Translate architecture and RTL requirements into PD objectives (synthesis, floorplan, placement, clock, routing, timing).
• Execute timing, power, extraction, physical-verification and signoff checks.
• Troubleshoot flow, timing, congestion, power, and physical-verification issues.
• Coordinate deliverables across architecture, RTL, verification, DFT, CAD, and manufacturing teams.
• Support automation and continuous improvement.

Conocimientos

ASIC PD

Floorplanning

Cross-functional teamwork

Educación

Bachelor's degree in Electrical/Electronics/Computer Engineering

Herramientas

EDA tools

Scripting (Python/TCL)

Descripción del empleo

Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.

People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip's nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values ; we affectionately refer to it as the Aggregate System and it's won us countless awards for diversity and workplace excellence.

Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.

Visit our careers page to see what exciting opportunities and company perks await!

Job Description:

Join the Physical Design team as a Engineer II-Physical Design supporting semiconductor synthesis, floorplanning, placement, clocking, routing, timing, power, physical verification, documentation, and tapeout-readiness activities. This role is best suited for candidates with 2.5-5 years of relevant experience in ASIC or SoC physical design, synthesis, floorplanning, place and route, timing closure, physical verification, or a closely related area.

In this role, you will independently execute defined physical-design assignments and coordinate assigned deliverables, partner with architecture, RTL design, verification, DFT, analog, package, methodology, CAD, product, test, manufacturing, and leadership teams, and help deliver robust performance, power, area, physical-verification closure, reliability, and tapeout readiness.

Responsibilities:

• Develop and maintain defined ASIC or SoC physical-design blocks, constraints, scripts, flows, and design data.
• Translate approved architecture and RTL requirements into synthesis, floorplan, placement, clock, routing, timing, power, and verification objectives.
• Execute implementation, regression, extraction, timing, power, physical-verification, and applicable signoff checks.
• Troubleshoot flow, constraint, timing, congestion, power, signal-integrity, physical-verification, and integration issues.
• Analyze reports, logs, results, defects, risks, dependencies, and technical tradeoffs; recommend actions.
• Maintain design configuration, scripts, run records, waiver evidence, release data, traceability, and technical documentation.
• Coordinate assigned deliverables across architecture, RTL design, verification, DFT, analog, package, methodology, CAD, product, test, and manufacturing teams.
• Support automation, reuse, corrective action, and continuous improvement.

Requirements/Qualifications:

Minimum qualifications: Bachelor's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, Computer Science, Physics, or a related field with 2.5-5 years of relevant experience in ASIC or SoC physical design, synthesis, floorplanning, placement, clock-tree synthesis, routing, extraction, static timing analysis, power integrity, physical verification, EDA flows, or closely related equivalent experience.

Qualified candidates should demonstrate analytical thinking, semiconductor physical-design judgment, structured problem solving, timing and power analysis, debugging and root-cause analysis, technical documentation, evidence-based communication, cross-functional collaboration, quality focus, and the ability to work with complex architecture, RTL, constraints, libraries, layout, timing, power, physical-verification, reliability, and manufacturing information.

Successful candidates are expected to demonstrate:

• Employment stability, reliability, and sustained accountability in prior roles.
• Effective teamwork and cross-functional collaboration.
• Integrity and accuracy in representing qualifications, experience, and credentials.

Preferred Qualifications:

• Experience with ASIC or SoC physical design, synthesis, floorplanning, placement, clock-tree synthesis, routing, extraction, static timing analysis, power integrity, or physical verification.
• Experience with EDA tools, scripting, automation, design constraints, low-power implementation, variation analysis, design-for-test, advanced process nodes, or tapeout flows.
• Experience resolving timing, congestion, power, signal-integrity, physical-verification, integration, reliability,