Physical Design Engineer

MaximaTek; New Jersey; On-site; USD 65,000 - 90,000; Full time

Job summary

MaximaTek is seeking a Physical Design Engineer to support development and implementation of high-performance semiconductor chips. The engineer will handle floorplanning, placement, CTS, routing, timing optimization, and physical verification.

This role welcomes entry-level candidates with backgrounds in VLSI, Electrical Engineering, Electronics Engineering, Computer Engineering, or related fields, as well as professionals with hands-on semiconductor physical design experience.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering or related field.
• Knowledge of VLSI/ASIC physical design concepts and digital logic.
• Familiarity with floorplanning, placement, CTS, routing, and timing analysis.

Responsibilities

• Develop and optimize floorplans, power plans, placement, CTS, routing, and timing.
• Perform synthesis and physical implementation using industry-standard EDA tools.
• Analyze and resolve setup and hold timing violations.
• Work on congestion, signal integrity, power, and area optimization.
• Perform CTS and clock optimization; support STA and timing closure.
• Analyze and resolve DRC, LVS, and connectivity violations; generate design reports.

Skills

Floorplanning

Placement

Timing analysis

Verilog/SystemVerilog

Scripting

Linux/Unix

Problem-solving

Education

Bachelor's or Master's in Electrical Engineering or Computer Engineering

Tools

Synopsys ICC2 / Fusion Compiler

Cadence Innovus

Synopsys Design Compiler

Cadence Tempus

Calibre

Job description

We are seeking a Physical Design Engineer to support the development and implementation of high-performance semiconductor chips. The engineer will work on physical implementation activities including floorplanning, placement, clock tree synthesis, routing, timing optimization, and physical verification.

This role is suitable for entry-level candidates with a background in VLSI, Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field, as well as professionals with hands‑on semiconductor physical design experience.

Key Responsibilities

• Develop and optimize floorplans, power plans, placement, CTS, routing, and timing.
• Perform synthesis and physical implementation using industry-standard EDA tools.
• Analyze and resolve setup and hold timing violations.
• Work on congestion, signal integrity, power, and area optimization.
• Perform clock tree synthesis (CTS) and clock optimization.
• Support static timing analysis (STA) and timing closure.
• Analyze and resolve physical design issues including DRC, LVS, and connectivity violations.
• Collaborate with RTL, synthesis, STA, DFT, verification, and backend teams.
• Generate and review physical design reports and implementation data.
• Support ECO implementation and design changes throughout the project.
• Participate in physical verification and tape‑out activities.
• Automate repetitive tasks using Tcl, Python, or Perl scripting.

Required Qualifications

• Bachelor's or Master's degree in:
• Electrical Engineering
• Computer Science with relevant VLSI coursework
• Related technical field
• Knowledge of VLSI/ASIC physical design concepts.
• Understanding of digital logic and semiconductor design flow.
• Familiarity with floorplanning, placement, CTS, routing, and timing analysis.
• Basic understanding of STA, DRC, LVS, and design constraints.
• Knowledge of Verilog/SystemVerilog is beneficial.
• Familiarity with Linux/Unix environments.
• Strong analytical and problem‑solving skills.

Preferred Skills

• Experience with EDA tools such as:
• Synopsys ICC2 / Fusion Compiler
• Cadence Innovus
• Synopsys Design Compiler
• Cadence Tempus
• Experience with Tcl/Python/Perl scripting.
• Knowledge of advanced semiconductor technology nodes.
• Exposure to physical verification tools such as Calibre.
• Understanding of PVT corners, timing libraries, parasitic extraction, and RC analysis.

Entry-Level Candidates

Candidates with 0–2 years of experience should ideally have academic or project experience in:

• Floorplanning and placement
• Clock Tree Synthesis
• Static Timing Analysis
• Physical verification
• EDA tools and scripting

Mid-Level Candidates

Candidates with 2–5 years of experience should have hands‑on experience with:

• Complete or significant portions of the physical design flow
• Timing closure
• Congestion and power optimization
• ECO implementation
• Physical verification
• EDA automation and scripting