Physical Design Engineer

Sintegra Inc.; Santa Clara (CA); On-site; USD 120,000 - 400,000; Full time

Job summary

An innovative semiconductor manufacturing company is seeking a Physical Design Verification Expert. This role involves conducting block-level designs, providing expert guidance on Cadence Pegasus, and mentoring team members. The ideal candidate will have a strong background in design, verification, and debugging, with proficiency in scripting languages like Tcl and Python. Join a forward-thinking team where your expertise will help shape the future of semiconductor design and verification processes, making a significant impact in a dynamic environment.

Qualifications

• Expertise in Cadence Pegasus for debugging and verification tasks.
• Proficiency in scripting with Tcl and Python for automation.

Responsibilities

• Conduct block-level design from Netlist-to-GDSII, including synthesis and signoff.
• Provide expert guidance on Cadence Pegasus usage for LVS and ERC debugging.

Skills

Cadence Pegasus

Tcl

Python

Synopsys Implementation tools

Multi-power domain design

Job description

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We are on the lookout for a highly specialized Physical Design Verification (PDV) Expert with rich experience in Cadence Pegasus. If you have a strong background in design, verification, and debugging, along with expertise in Pegasus, we’d love to connect with you!

Key Responsibilities:

• Conduct block-level design from Netlist-to-GDSII, including synthesis, floor-planning, place & route, timing/EMIR, and signoff.
• Execute structural implementation tasks such as datapaths, bus planning, and routing.
• Provide expert guidance on Cadence Pegasus usage for tasks like debugging LVS and ERC issues.
• Lead efforts to integrate and optimize PDV workflows using Pegasus.
• Collaborate with and mentor team members to build Pegasus expertise within the organization.

Required Skills and Qualifications:

• Proficiency with Synopsys Implementation tools.
• Solid scripting skills in Tcl and Python.
• Extensive experience with multi-power domain design.
• Expert-level knowledge of Cadence Pegasus, with hands-on experience in debugging and verification tasks (LVS and ERC).
• Ability to teach and support others in using Pegasus effectively.

Seniority level

• Seniority level

  Mid-Senior level

Employment type

• Employment type

  Full-time

Job function

• Industries

  Semiconductor Manufacturing

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