Staff RTL Design Engineer

Acceler8 Talent; San Francisco (CA); Remote; USD 225,000 - 250,000; Full time

Job summary

Join a forward-thinking company as a Staff ASIC Design Engineer, where you'll lead innovative design processes for high-performance systems. This fully remote role offers the chance to work on cutting-edge technology, collaborating with top-tier teams to tackle complex challenges in the AI hardware space. With a strong focus on developing efficient interconnect architectures, your expertise will be crucial in shaping the future of data processing solutions. If you're passionate about making a significant impact in a rapidly growing field, this opportunity is perfect for you.

Qualifications

• Proven experience with large, complex SoCs is essential.
• Strong background in high-performance design and verification.

Responsibilities

• Lead design processes from analysis to implementation.
• Collaborate with teams to develop high-throughput engines.

Skills

Designing high-performance interface logic

Expertise in PCIe Gen5/6 and CXL

Designing multi-threaded datapaths

Strong knowledge of SystemVerilog

Proficiency in Python

Proficiency in Perl

Education

BSEE/CE

MSEE/CE

Job description

1 week ago Be among the first 25 applicants

This range is provided by Acceler8 Talent. Your actual pay will be based on your skills and experience — talk with your recruiter to learn more.

Base pay range

$225,000.00/yr - $250,000.00/yr

Direct message the job poster from Acceler8 Talent

Recruiting the top AI Hardware Engineers in the world.

Acceler8 Talent has partnered with a Nvidia backed data center acceleration company that is actively searching for a driven Staff ASIC Design Engineer.

This company is deeply committed to developing a novel interconnect architecture aimed at resolving congestion challenges within extensively distributed systems. Their recent successful completion of a significant Series B funding round serves as a strong indicator of their growth and potential.

The company's founding members bring substantial expertise from distinguished hardware and technology enterprises. Notably, their primary investor boasts an admirable track record of nurturing early-stage startups into prosperous and thriving enterprises.

They are currently seeking an engineer with a high level of expertise with large, complex, SoCs.

If you are located in the San Francisco Bay Area, Austin, TX, Raleigh, NC, or Boston, MA, area this company is offering a fully remote position.

Roles and Responsibilities:

• Lead all stages of the design process, from tradeoff analysis and specification to RTL implementation.
• Deliver high-performance designs that meet timing, area, reliability, testability, and power targets set by the engineering team.
• Collaborate with system software, architecture, and microarchitecture teams to develop high-throughput engines for data processing, movement, storage, and scheduling.
• Support functional verification, including strategy development, test planning, and execution.
• Assist with silicon bring-up and post-silicon testing of critical functions.

Skills/Qualifications:

• Proven experience designing high-performance interface logic or processing pipelines (e.g., PCIe, CXL, NV-Link, Ethernet, Infiniband) in advanced silicon geometries.
• Preferred experience with PCIe Gen5/6 and CXL at the Transaction Layer.
• Expertise in designing multi-threaded datapaths and blocks like DMA controllers and queueing engines.
• Strong knowledge of SystemVerilog.
• Proficiency in Python, Perl, or other scripting languages.

Experience:

• Junior: BSEE/CE + 3 years or MSEE/CE + 2 years.
• Mid: BSEE/CE + 7 years or MSEE/CE + 5 years.

If you feel this is relevant to your skillset and the work you have done in the industry please apply here. If you don't have any experience with large, complex SoCs please do not apply.

Seniority level

• Seniority level

  Mid-Senior level

Employment type

• Employment type

  Full-time

Job function

• Industries

  Computer Hardware Manufacturing

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