Physical Design Engineer

LeadStack Inc.; San Jose (CA); Hybrid; USD 200,000 - 250,000; Full time

Job summary

An established industry player is on the lookout for a skilled Physical Design Engineer to join their innovative design team. In this dynamic role, you'll be instrumental in the physical design of cutting-edge mobile applications, ensuring seamless transitions from synthesized gates to GDS delivery for tapeout. With a focus on advanced nodes and extensive experience with Synopsys tools, you will enhance methodologies and manage complex projects. This is a fantastic opportunity to contribute to impactful designs in a collaborative environment, where your expertise will shape the future of technology.

Qualifications

• 5+ years of relevant experience in physical design engineering.
• Expertise in place and route processes and tapeout sessions.

Responsibilities

• Manage physical design from synthesized gates to GDS delivery.
• Perform physical implementation using Synopsys ICC2.

Skills

Physical Design

Place and Route

Tapeout Processes

Synopsys Tools (ICC2)

Calibre DRC/LVS

TCL Scripting

Layout Automation

Timing Constraints

Education

Bachelor’s degree in Computer Engineering

Bachelor’s degree in Electrical Engineering

Tools

Synopsys ICC2

Calibre

Perl

Python

Tcl

Job description

This range is provided by LeadStack Inc.. Your actual pay will be based on your skills and experience — talk with your recruiter to learn more.

Base pay range

$75.00/hr - $85.00/hr

Direct message the job poster from LeadStack Inc.

Senior Technical Recruiter - Helping you find your next opportunity!

Job Title: Physical Design Engineer (SoC)

Duration: 06 Months

Location: San Jose, CA 95134 – Hybrid 3 Days a week

Pay Range: $75 - $85/hour on W2

Job Description:

We are seeking a results-oriented Physical Design Engineer (Contractor) to join our design team. You will work on the physical design of cutting-edge mobile applications, taking designs from synthesized gates to GDS delivery for tapeout. Key responsibilities include expertise in place and route, tapeout sessions, and managing multiple blocks across 28nm, 14nm, and 8nm nodes. Must have extensive experience with Synopsys physical design tools (ICC2), Calibre DRC/LVS, and Star-RC extraction. Experience with timing, functional ECO, low-power implementation, TCL scripting, and layout automation is essential.

Requirements:

• 5+ years of relevant experience.
• Bachelor’s degree in Computer Engineering, Electrical Engineering, or related fields.
• Strong knowledge of physical design, place and route, and tapeout processes.
• Experience with advanced nodes (16nm and below).
• Proficiency with Synopsys tools, Calibre, scripting languages (Perl, Python, Tcl), and automation.
• Understanding of implementation flow and timing constraints.

Additional Responsibilities:

• Perform physical implementation using Synopsys ICC2.
• Develop and maintain tool flows supporting projects.
• Enhance physical design methodologies.

Seniority level

• Mid-Senior level

Employment type

• Contract

Job function

• Engineering, Manufacturing, and Design

Industries

• IT Services and Consulting, Semiconductor Manufacturing, Electrical and Electronics Manufacturing