Physical Design Engineer

Central Business Solutions, Inc; San Jose (CA); Remote; USD 200,000 - 250,000; Full time

Job summary

An established industry player is seeking a skilled Physical Design Engineer to join their innovative team. In this long-term contract role, you will be responsible for developing and implementing physical design strategies for multi-hierarchy low-power designs. Your expertise in RTL2GDSII flow and advanced technology nodes will be crucial in delivering high-quality designs. This remote position offers a unique opportunity to work on cutting-edge projects, resolve complex design issues, and contribute to the integration of ASIC/SoC designs. If you have a passion for physical design and want to make a significant impact in the field, this role is perfect for you.

Qualifications

• 5+ years of experience in physical design with a Bachelor's in Electrical Engineering.
• Strong understanding of RTL2GDSII flow and low power implementation.

Responsibilities

• Develop and own physical design implementation for low-power designs.
• Resolve design issues and drive execution for physical design.

Skills

Physical Design Implementation

Low Power Design

Static Timing Analysis

Design for Testability

Problem Solving

Education

Bachelor's degree in Electrical Engineering

Tools

DC/Genus

ICC2/Innovus

Primetime

Redhawk/Voltus

Calibre

Job description

Title: Physical Design Engineer
Location: 100% Remote
Duration: Long Term Contract role

Responsibilities

• Develop and own physical design implementation of multi-hierarchy low-power designs including physical-aware logic synthesis, design for testability, floorplan, place and route, static timing analysis, IR Drop, EM, and physical verification in advanced technology nodes.
• Resolve design and flow issues related to physical design, identify potential solutions, and drive execution
• Deliver physical design of an end-to-end IP or integration of ASIC/SoC design

Minimum Qualifications:

• Bachelor's degree in Electrical Engineering, with 5 years of relevant physical design experience
• Strong understanding in the RTL2GDSII flow and design tapeouts in 16nm/14nm or below process technologies
• Experience with low power implementation, power gating, multiple voltage rails, strong UPF/CPF knowledge.
• Experience working with most EDA tools like DC/Genus, ICC2/Innovus, Primetime, Redhawk/Voltus, Calibre.

Preferred Qualification:

• Experience in running physical-aware logic synthesis and achieving optimal synthesis QoR on low power designs
• Knowledge of static timing analysis and concepts, defining timing constraints and exceptions, corners/voltage definitions.
• Experience in Block-level and Full-chip floor-planning, power grid planning
• Experience with custom or regular clock tree synthesis implementation at block level or top level, and clock power reduction techniques.
• Experience with Python, TCL, Perl programming.