Physical Design Architect: RTL-to-GDSII Automation

Etched; San Jose (CA); On-site; USD 170,000 - 230,000; Full time

Benefits offered by this job

Medical/dental/vision package

Housing subsidy

Relocation support

Wellness benefits

Daily lunch/dinner in office

Unlimited compute budget

Job summary

Etched is building a new category of AI hardware and seeks a Physical Design Methodology Engineer to architect and own the PD flow from first principles. You will enable rapid design iteration, accelerate time-to-market, and drive PPA gains through state-of-the-art CAD methodologies.

You will lead automated RTL-to-GDSII flows, manage tool configurations, and build a robust CAD infrastructure, partnering with block owners to deliver convergent timing and signoff readiness in a fast-paced,

Qualifications

• 5-10+ years of PD or PD methodology/CAD experience.
• Experience building automated RTL-to-GDSII flows used by multiple block owners.
• Experience creating block-level and full-chip PG mesh from scratch with DRD/EM/IR analysis.
• Experience with DRC-clean floorplanning and automated checks.
• Experience with Cadence/Simulators or Synopsys tools for RTL-to-GDSII flows.
• PPA tuning and timing correlation across pre-route, post-route, and signoff.
• Experience integrating sign-off tools into production flows.
• Back-end design experience on advanced process nodes (5nm and below).
• Familiarity with UPF-based low-power design and multi-Corner setups.
• Strong Tcl and Python for flow development and automation.

Responsibilities

• Architect, build, and maintain automated RTL-to-GDSII flow from synthesis to signoff.
• Automate PD flows end-to-end, including regression, run management, and release of configurations.
• Develop and maintain CAD infrastructure for PD with tool qualification and deployments.
• Create dashboards tracking PD project timing, verification, and utilization trends.
• Optimize tool flows and evaluate latest features with EDA vendors.
• Define flow reference, QoR targets, and delivery checklists for third-party services.
• Collaborate with owners to debug flow issues and encode fixes into methodology.
• Create block and full-chip PG mesh using DRD documents, EM/IR feedback.
• Maintain a DRC-clean floorplanning flow and floorplan signoff checks.
• Drive PPA tuning to improve power, performance, and area outcomes.
• Establish timing correlation from pre-route through signoff tools.

Skills

PD CAD

RTL-to-GDSII

Python

Tcl

Automation

EDA tooling

Floorplanning

EM/IR analysis

PPA tuning

Automation scripting

Tools

Cadence Innovus

Cadence Genus

Synopsys Fusion Compiler

PrimeTime

Tempus

Voltus

Calibre

Job description

Etched is building a new category of AI hardware and seeks a Physical Design Methodology Engineer to architect and own the PD flow from first principles. You will enable rapid design iteration, accelerate time-to-market, and drive PPA gains through state-of-the-art CAD methodologies.

You will lead automated RTL-to-GDSII flows, manage tool configurations, and build a robust CAD infrastructure, partnering with block owners to deliver convergent timing and signoff readiness in a fast-paced,