Senior Physical Design Engineer - Frontier AI Chips

The Consensus; San Jose (CA); On-site; USD 180,000 - 240,000; Full time

Benefits offered by this job

Medical, dental, and vision packages

$500 per month credit for waiving med

Housing subsidy $2000 per month near a

Relocation support to San Jose (Santan

Wellness benefits

Daily lunch and dinner in office

Unlimited compute budget

Job summary

Etched is building a new category of AI hardware; as the top-level PD engineer you will own full-chip implementation from floorplanning to GDSII, driving PPA optimization and timing closure. You will collaborate with RTL designers to iterate rapidly and ensure successful tapeouts.

Lead clocking across all corners, manage top-level timing closure, and own PV at block and full-chip levels. Strong Cadence/Synopsys flows and scripting proficiency are essential for success in our fast-paced,

Qualifications

• 10+ years of chip planning and top-level PD experience.
• Experience with full-chip closure on 5nm or below.
• Experience with Cadence Innovus or Synopsys Fusion Compiler RTL-to-GDSII flows.
• Experience with Synopsys PrimeTime and Cadence Tempus for timing signoff.
• Experience with Pegasus or Calibre for physical verification signoff.
• Experience with hierarchical timing budgeting, constraint management, and ECO closure.
• Experience with Cadence Innovus for top-level assembly, routing, and layout fixes.
• Deeply creative and able to think from first principles.

Responsibilities

• Own full-chip clocking across all PVT corners and modes.
• Manage MMMC timing closure at the top level.
• Own timing constraints and hierarchical timing budgeting between top level and blocks.
• Drive functional and timing ECO closure and achieve final timing signoff for tapeout.
• Own end-to-end physical verification closure at block, sub-system, and full-chip level across DRC, LVS, ERC, antenna, density, fill, and top-level integration.
• Debug complex PV violations across layout, routing, macros, IP, power grid, rule decks, and tool or setup issues, and fix violations directly in layout using Innovus.
• Build a repeatable, tapeout-ready PV methodology with clean runs, waiver discipline, version control, triage, and final signoff reviews.

Skills

Chip planning

Top-level PD

Floorplanning

Clocking

Timing closure

PV debugging

Innovus

Genus

PrimeTime

Tempus

Tools

Innovus

Genus

Fusion Compiler

PrimeTime

Tempus

Calibre

Job description

Etched is building a new category of AI hardware; as the top-level PD engineer you will own full-chip implementation from floorplanning to GDSII, driving PPA optimization and timing closure. You will collaborate with RTL designers to iterate rapidly and ensure successful tapeouts.

Lead clocking across all corners, manage top-level timing closure, and own PV at block and full-chip levels. Strong Cadence/Synopsys flows and scripting proficiency are essential for success in our fast-paced,