PCIe Validation Engineer

HCLTech; Sunnyvale (CA); On-site; USD 78,000 - 148,000; Full time

Job summary

HCLTech in Sunnyvale, CA seeks a PCIe Engineer to design, validate, and bring up PCIe IP and SoC platforms. You will develop tests, run pre-silicon verification, and collaborate with cross-functional teams to ensure robust PCIe implementations.

The candidate will work with integration teams, use VIP environments, perform silicon bring-up on FPGA/emulation, and drive PCIe compliance testing per PCI-SIG specs.

Qualifications

• Education: B.S./M.S./Ph.D. in Electrical Engineering, Computer Engineering, or related field.
• Experience: 3–8+ years of PCIe validation, verification, or silicon bring-up.
• Strong PCIe knowledge across Gen3–Gen6 including: Transaction Layer, Data Link Layer, and Physical Layer.
• Proficiency in SystemVerilog/UVM for pre-silicon test development.
• Experience with protocol analyzers and lab debug tools.
• Familiarity with scripting languages (Python, Perl, Tcl).
• Understanding of PCIe enumeration, BAR programming, and configuration space.
• Experience with FPGA prototyping or emulation is a plus.

Responsibilities

• Develop and execute test plans for PCIe IP blocks and SoC integration.
• Create directed and constrained-random tests for TLP, DLLP, and PHY functionality.
• Perform protocol-level analysis using VIP environments and bus functional models.
• Debug RTL-level issues related to link training, ASPM, L-states, equalization, and error handling.
• Collaborate with design teams on coverage closure, assertions, and functional coverage models.
• Bring up and validate PCIe links on silicon platforms (FPGA, emulation, first silicon).
• Develop and execute post-silicon validation test plans covering training, enumeration, data integrity, error injection, and compliance.
• Debug silicon-level issues using protocol analyzers, oscilloscopes, and logic analyzers.
• Characterize PCIe PHY performance including jitter, eye diagrams, and signal integrity.
• Collaborate with platform, firmware, and BIOS teams to resolve system-level PCIe issues.
• Drive compliance and interoperability testing per PCI-SIG specifications.
• Automate test infrastructure, result parsing, and regression frameworks.
• Document findings, debug methodologies, and test coverage metrics.
• Contribute to team knowledge sharing.

Skills

SystemVerilog/UVM

PCIe Gen3-Gen6

Protocol analyzers

Python

Perl

Tcl

FPGA prototyping

Lab debug tools

PCIe enumeration/config space

Education

B.S./M.S./Ph.D. in Electrical Engineering, Computer Engineering, or related field

Tools

Emulation platforms

PCIe debugging tools

Job description

HCLTech in Sunnyvale, CA seeks a PCIe Engineer to design, validate, and bring up PCIe IP and SoC platforms. You will develop tests, run pre-silicon verification, and collaborate with cross-functional teams to ensure robust PCIe implementations.

The candidate will work with integration teams, use VIP environments, perform silicon bring-up on FPGA/emulation, and drive PCIe compliance testing per PCI-SIG specs.