PCIe Gen6 Verification Engineer

ACL Digital; San Jose (CA); On-site; USD 120,000 - 180,000; Full time

Job summary

ACL Digital is seeking a PCIe verification engineer in San Jose, CA to verify a Gen6 subsystem using SystemVerilog/UVM. You will develop plans, testbenches, cases, and coverage, and ensure protocol compliance across LTSSM, link training, and power management.

Work with RTL, Architecture, and Validation teams to drive regression suites, debug issues, and achieve coverage closure for a complex PCIe design.

Qualifications

• Strong SystemVerilog/UVM expertise.
• Experience with PCIe VIPs, SVA, and coverage closure.
• Proficiency with simulators and scripting (Python/Perl/Shell).

Responsibilities

• Verify the PCIe Gen6 subsystem using SystemVerilog/UVM.
• Develop verification plans, testbenches, test cases, assertions, and functional coverage.
• Verify LTSSM, Link Training, FLIT mode, Flow Control, Error Handling, Power Management, and PCIe protocol compliance.
• Integrate PCIe VIPs, execute regressions, debug failures, and drive coverage closure.
• Collaborate with RTL, Architecture, and Validation teams through verification signoff.

Skills

SystemVerilog/UVM expertise

PCIe VIPs experience

SVA assertions

Constrained-random verification

Coverage closure

Scripting (Python/Perl/Shell)

Debugging and communication skills

Tools

Xcelium

VCS

Questa

Job description

ACL Digital is seeking a PCIe verification engineer in San Jose, CA to verify a Gen6 subsystem using SystemVerilog/UVM. You will develop plans, testbenches, cases, and coverage, and ensure protocol compliance across LTSSM, link training, and power management.

Work with RTL, Architecture, and Validation teams to drive regression suites, debug issues, and achieve coverage closure for a complex PCIe design.