Lead Software Engineer - PCIe Verification IP

Cadence Design Systems; San Jose (CA); On-site; USD 114,800 - 213,200; Full time

Benefits offered by this job

Paid vacation

401(k) plan with employer match

Employee stock purchase plan

Job summary

Cadence Design Systems is seeking a Lead Software Engineer to join their PCIe Verification IP team in San Jose, California. You will be responsible for software development and validation, collaborating with a diverse team on IP development, and interacting with customers to resolve issues.

The ideal candidate has extensive experience in C/C++, strong problem-solving skills, and a background in object-oriented programming. Attractive benefits and salary range apply.

Qualifications

• Minimum of 4 years of experience for BS, 2 years for MS, or a new PhD graduate.
• Experience modeling in C/C++, and a background in algorithms.
• Outstanding analytical and problem-solving skills.

Responsibilities

• Software development and validation of PCIe Verification IP.
• Collaborate with diverse teams on PCIe product development.
• Work with customers to resolve implementation issues.

Skills

C/C++ modeling

Object-oriented programming

Problem-solving skills

Communication skills

Education

BS or MS with relevant experience or new PhD

Tools

Verilog/SystemVerilog

Job description

Cadence Design Systems is seeking a Lead Software Engineer to join their PCIe Verification IP team in San Jose, California. You will be responsible for software development and validation, collaborating with a diverse team on IP development, and interacting with customers to resolve issues.

The ideal candidate has extensive experience in C/C++, strong problem-solving skills, and a background in object-oriented programming. Attractive benefits and salary range apply.