Senior Design Verification Engineer

ACL Digital; San Jose (CA); On-site; USD 140,000 - 190,000; Full time

Job summary

ACL Digital in the United States is seeking a verification engineer to advance PCIe Gen6 validation on-site in either Austin, TX or San Jose, CA. You will develop verification plans, testbenches, test cases, and coverage to ensure protocol compliance.

The ideal candidate has strong SystemVerilog/UVM expertise, experience with PCIe VIPs and assertions, and proficient scripting (Python/Perl/Shell). You will integrate VIPs, run regressions, debug failures, and collaborate with RTL and Validation

Qualifications

• Strong SystemVerilog and UVM experience for validation environments.
• Experience with PCIe VIPs, assertions (SVA), constrained-random verification, and coverage.
• Proficiency with simulators (Xcelium/VCS/Questa) and scripting (Python/Perl/Shell).
• Excellent debugging and communication skills.

Responsibilities

• Verify PCIe Gen6 subsystem using SystemVerilog/UVM and develop test plans.
• Develop verification plans, testbenches, test cases, assertions, and coverage.
• Verify LTSSM, Link Training, Flow Control, and protocol compliance.
• Integrate PCIe VIPs, run regressions, debug failures, and drive coverage closure.
• Collaborate with RTL, Architecture, and Validation teams through verification signoff.

Skills

SystemVerilog

UVM

Debugging

Communication

Tools

PCIe VIPs

Xcelium

VCS

Questa

Python

Perl

Shell

Job description

Location: Austin, TX or San Jose, CA (Onsite)

Duration: Long term Contact

Responsibilitie

• sVerify the PCIe Gen6 subsystem using SystemVerilog/UVM
• .Develop verification plans, testbenches, test cases, assertions, and functional coverage
• .Verify LTSSM, Link Training, FLIT mode, Flow Control, Error Handling, Power Management, and PCIe protocol compliance
• .Integrate PCIe VIPs, execute regressions, debug failures, and drive coverage closure
• .Collaborate with RTL, Architecture, and Validation teams through verification signoff

Required Skill

• sStrong SystemVerilog/UVM expertise
• .Experience with PCIe VIPs, assertions (SVA), constrained-random verification, and coverage closure
• .Proficiency with Xcelium/VCS/Questa and scripting (Python/Perl/Shell)
• .Good debugging and communication skills