PCBA DFT & Testability Lead — Boundary Scan Expert

Celestica; Fort Worth, Arlington, Dallas (TX, TX, TX); On-site; USD 120,000 - 165,000; Full time

Benefits offered by this job

Equal Opportunity Employer

E-Verify employer

Job summary

Celestica is seeking a Hardware DFT & Testability Engineer (PCBA) to ensure testability and maximum coverage are embedded into PCB hardware designs early in the design cycle. This upstream pre-layout gatekeeper role focuses on ICT access, boundary scan chains, and MTRS-driven coverage models.

The successful candidate will audit schematics, drive testability decisions, and collaborate with hardware, PCB layout, and software teams to deliver high-yield, debug-ready releases.

Qualifications

• 4+ years of experience in PCBA DFT, ICT, or manufacturing test engineering.
• Bachelor's degree in Electrical or Electronic Engineering.
• Strong knowledge of boundary scan (IEEE 1149.1) and testability reviews.

Responsibilities

• Perform pre-freeze audits of schematics vs DFT rules and test point access.
• Model MTRS coverage and identify gaps before manufacturing.
• Dispositon findings with design teams to add test points and boundary scan.
• Verify coverage on the first ICT/flying-probe fixture and document gaps.
• Assist with functional test definitions and early build debug on the manufacturing floor.

Skills

PCBA DFT

ICT Testing

IEEE 1149.1 Boundary Scan

PCB Layout Review

Education

Bachelor's degree in Electrical Engineering

Tools

Keysight 3070

Teradyne TestStation

Flying probe

Job description

Celestica is seeking a Hardware DFT & Testability Engineer (PCBA) to ensure testability and maximum coverage are embedded into PCB hardware designs early in the design cycle. This upstream pre-layout gatekeeper role focuses on ICT access, boundary scan chains, and MTRS-driven coverage models.

The successful candidate will audit schematics, drive testability decisions, and collaborate with hardware, PCB layout, and software teams to deliver high-yield, debug-ready releases.