Prinicipal DFT Engineer

Celero Communications; Irvine (CA); On-site; USD 120,000 - 190,000; Full time

Job summary

Celero Communications is seeking a talented DFT Engineer to join our silicon engineering organization. You will partner with design, verification, physical design, product, and manufacturing teams to implement robust DFT methodologies that enable high quality, high volume production of complex ASIC and SoC products.

As a DFT Engineer, you will develop and implement DFT architecture for ASIC/SoC designs, perform scan insertion, planning, and compression, generate ATPG patterns, and verify MBIST

Qualifications

• Bachelor’s degree in Electrical or Computer Engineering or related field.
• 8+ years of ASIC/SoC DFT experience.
• Strong understanding of scan, ATPG, fault models, and test coverage methodologies.
• Experience with industry tools such as TestMAX, Tessent, and Modus.
• Proficiency in Verilog/SystemVerilog and digital design fundamentals.
• Linux experience with Python, Tcl, Perl, or Shell scripting.
• Results-driven engineer with strong debugging abilities.

Responsibilities

• Develop and implement DFT architecture for ASIC and SoC designs.
• Perform scan insertion, scan chain planning, and scan compression implementation.
• Generate and validate ATPG patterns and analyze fault coverage results.
• Implement and verify MBIST and other on-chip test features.
• Collaborate with RTL, verification, and physical design teams for DFT integration.
• Support JTAG and boundary-scan implementation and debugging.
• Lead DFT sign-off activities and manufacturing test readiness.
• Participate in silicon bring-up, failure analysis, and yield improvement efforts.

Skills

ATPG

Scan insertion

Fault models

Test coverage

Debugging

Cross-functional

Education

Bachelor’s degree (EE/CE)

Tools

Synopsys TestMAX/TetraMAX

DFT Compiler

Siemens Tessent

Cadence Modus

Equivalent tools

Job description

Celero Communications is seeking a talented DFT Engineer to join our silicon engineering organization. This individual will partner with design, verification, physical design, product, and manufacturing teams to implement robust Design-for-Test methodologies that enable high quality, high volume production of complex ASIC and SoC products.

What You Will Do

• Develop and implement DFT architecture for ASIC and SoC designs.
• Perform scan insertion, scan chain planning, and scan compression implementation.
• Generate and validate ATPG patterns and analyze fault coverage results.
• Implement and verify MBIST, and other on-chip test features.
• Collaborate with RTL, verification, and physical design teams to ensure successful DFT integration.
• Support JTAG and boundary-scan implementation and debug.
• Drive DFT signoff activities and manufacturing test readiness.
• Participate in silicon bring-up, failure analysis, and yield improvement efforts.

What You Will Bring

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field.
• 8+ years of ASIC/SoC DFT experience.
• Strong understanding of scan, ATPG, fault models, and test coverage methodologies.
• Experience with Synopsys TestMAX/TetraMAX, DFT Compiler, Siemens Tessent, Cadence Modus, or equivalent tools.
• Knowledge of Verilog/SystemVerilog and digital design fundamentals.
• Experience in Linux and scripting using Python, Tcl, Perl, or Shell.
• Results-driven engineer with strong debugging abilities.
• Comfortable working in fast-paced cross-functional environments.
• Passion for delivering high-quality silicon products.

Preferred Qualifications

• Experience with advanced-node semiconductor technologies.
• Hands-on experience with MBIST, compression architectures, and JTAG.
• Knowledge of timing closure, physical design impacts, and low-power design techniques.