Packaging Engineer

Socket.dev; California (MO); On-site; USD 150,000 - 230,000; Full time

Job summary

Socket.dev is seeking a senior IC packaging engineer to develop Custom Silicon packaging solutions in modules/systems for consumer markets. You will interface across design, quality, supply chain, and suppliers to deploy new packaging technologies.

Preferred candidates hold MS/PhD and 10+ years of IC packaging experience, with hands-on knowledge of WLP, Wafer Bumping, and BEOL processes, plus strong DOE and reliability testing skills.

Qualifications

• BS degree with 10+ years of IC packaging experience.
• MS/PhD in mechanical engineering, physics, materials science or similar preferred.
• Experience with Wafer Level Packaging (WLP), Wafer Bumping, and BEOL assemblies.
• Strong knowledge of reliability testing and DOE.

Responsibilities

• Interface between internal design, quality, supply chain, and external suppliers to develop packaging technologies.
• Drive development cycles to enable high-volume manufacturing.
• Present concepts and data at team and executive reviews.
• Collaborate across functions to optimize packaging reliability and yield.

Education

BS

MS/PhD in mechanical engineering, physics, materials science or similar

Tools

AutoCAD

APD

Multi-physics simulation

Job description

Looking for a senior level IC packaging engineer to develop exciting new products. You will be responsible providing Custom Silicon packaging solutions in a module/system for various consumer markets.

Description

• In this fast-paced environment, your role is to interface between internal product/device design, quality, supply chain, and the external suppliers to develop and deploy new packaging technologies.
• Must be a good negotiator and influencer to drive industry to meet company needs.
• We are looking for individuals who are very innovative with a proven track record to reduce package development cycle and qualify devices into a high-volume manufacturing environment.

Minimum Qualifications

BS and 10+ years of relevant industry experience.

Preferred Qualifications

M.S or Ph.D. degree in mechanical engineering, physics, materials science or similar disciplines with a minimum of 10 years of experience in IC packaging. AutoCAD, APD and multi-physics simulation knowledge is a plus.Industry experience and work on WLP either in IDM or Fabless companies. Knowledge and hands-on experience on Wafer Bumping and Dielectric materials and their pros/cons is a must.Some hands-on knowledge in Manufacturing assembly processes; such as wafer back-grind, wafer dicing, Flip Chip die attach, encapsulation/molding, under-fill, ball attach, package singulation and Tape & Reel. In-depth knowledge in Wafer Level Chip Scale Packaging (RDL/Wafer Bumping & BEOL Assembly processes for Fan-In & Fan-Out designs). Good knowledge on Package Qualification and Reliability testing.Expert level knowledge of common reliability failure modes. Able to understand device physics and component/board level reliability testing. Proven track record to bring a product/package from conceptual stage to development and to HVM environment. Ability to construct Designs of Experiments and down-select materials and processes.Good written and verbal communication skills. Able to present ideas, design concepts, data and plan with high confidence at team meetings and executive review meetings.Able to perform independent research and development work with minimal supervision.