Package Design Engineer: Signal & Power Integrity

Teradyne; North Reading (MA); On-site; USD 111,000 - 178,000; Full time

Benefits offered by this job

Discretionary bonus

Comprehensive benefits

Tuition assistance programs

Job summary

Teradyne is seeking a Package Design Engineer with an electrical engineering foundation to support our advanced measurement ASIC products in the Semiconductor Test Division. You will work across chip, package, board interconnects, and collaborate with ASIC, PCB, thermal, mechanical, and supplier teams to develop analysis approaches and practical design solutions.

Candidates should have a BSEE and 2+ years in semiconductor packaging or high-speed hardware, with experience in signal integrity,

Qualifications

• BSEE or closely related electrical engineering discipline.
• 2+ years in semiconductor packaging, high-speed hardware, signal integrity, or related field.
• Working knowledge of EM/ transmission-line fundamentals, impedance control, reflections, crosstalk, and power-distribution concepts.
• Experience with time-domain and frequency-domain analysis, S-parameters, circuit simulation, or EM field solvers.
• Familiarity with package and PCB design concepts, fabrication, and design-for-manufacture considerations.

Responsibilities

• Support ASIC package signal and power integrity development, including stackup evaluation and escape planning.
• Develop and review package/PCB layout constraints for high-speed links and interfaces.
• Apply EM and transmission-line principles to evaluate interconnects in time and frequency domains.
• Build, review, and document simulation models (insertion loss, return loss, crosstalk, eye diagrams).
• Plan and support PDN analysis, including impedance, decoupling, and transient droop.
• Collaborate with ASIC/PCB/thermal/mechanical teams and suppliers to mitigate risks.
• Contribute to design-for-manufacture/assembly reviews for substrates and PCBs.
• Prepare design-review materials, analysis summaries, and requirements.

Skills

Signal integrity

Power integrity

High-speed signaling

PCB design

Collaborative teamwork

Analytical skills

Education

Bachelor of Science in Electrical Engineering (BSEE)

Tools

Cadence tools

Ansys

HFSS

SPICE

Python

MATLAB

VNA

Job description

Teradyne is seeking a Package Design Engineer with an electrical engineering foundation to support our advanced measurement ASIC products in the Semiconductor Test Division. You will work across chip, package, board interconnects, and collaborate with ASIC, PCB, thermal, mechanical, and supplier teams to develop analysis approaches and practical design solutions.

Candidates should have a BSEE and 2+ years in semiconductor packaging or high-speed hardware, with experience in signal integrity,