ASIC Packaging Signal/Power Integrity Hardware Engineer [Hybrid]

Anysilicon; San Jose (CA); Hybrid; USD 120,000 - 170,000; Full time

Job summary

Cisco Silicon One is seeking an ASIC Packaging Signal/Power Integrity Hardware Engineer to join its ASIC team in a hybrid role in San Jose, CA. The position focuses on developing and verifying next-generation ASIC packaging to ensure high-speed signaling and robust power integrity across Cisco platforms.

Responsibilities include drafting design rules for ultra-high-speed signaling, performing SI/PI analyses, and coordinating with layout teams and vendors to achieve reliable, high-volume

Qualifications

• Bachelor's or higher in Electrical Engineering with relevant experience.
• Experience with high-speed design principles and impedance network analysis.
• Proficiency in pre- and post-layout SI/PI simulations using Cadence Sigrity and Ansys HFSS.
• Experience conducting layout reviews and physical design validation using Cadence APD.

Responsibilities

• Develop, document, and implement design rules for ultra-high-speed signaling.
• Analyze substrate SI/PI and collaborate with the layout team for optimal solutions.
• Design and develop ASIC packages for high-volume release, including post-layout extraction and reporting.
• Collaborate with system partners and vendors to resolve technical issues and achieve power and signal integrity.

Skills

High-Speed Design & Theory

Layout Review & Physical Validation

Education

Bachelor's degree in Electrical Engineering

Tools

Cadence Sigrity

Ansys HFSS

Cadence APD

Job description

ASIC Packaging Signal/Power Integrity Hardware Engineer [Hybrid]

Cisco Silicon One is seeking a Signal and Power Integrity Engineer to join their specialized ASIC team in San Jose, CA. This role involves developing and verifying next-generation ASIC packaging for various Cisco platforms, ensuring high-speed signaling and power integrity across complex networks.

Responsibilities:

• Develop, document, and implement design rules for ultra-high-speed signaling.


• Analyze substrate signal integrity (SI) and power integrity (PI) and collaborate with the layout team for optimal solutions.


• Design and develop ASIC packages for high-volume release, including post-layout extraction and reporting.


• Collaborate with system partners and vendors to resolve technical issues and achieve combined power and signal integrity.

Qualifications:

• Bachelor's degree in Electrical Engineering with 4 years of relevant experience, or a Master's degree with 2 years, or a PhD with no experience, or equivalent work experience.


• Experience with high-speed design principles, including Transmission Line Theory and impedance network analysis.


• Proficiency in pre- and post-layout SI/PI simulations using EDA tools like Cadence Sigrity and Ansys HFSS.


• Experience conducting layout reviews and physical design validation using Cadence APD.

Skills:

• High-Speed Design & Theory


• Layout Review & Physical Validation