Optical Design Engineer, Silicon Photonics Innovation

Cisco Systems; Carlsbad (CA); On-site; USD 140,000 - 250,000; Full time

Benefits offered by this job

Annual bonuses

Cisco stock units (RSUs)

401(k) with company match

Paid holidays

Job summary

Cisco Systems in California seeks a senior Silicon Photonics engineer to lead the full design cycle from photonic simulations to layout and tapeout, collaborating with EIC and module teams to deliver integrated opto-electronic chipsets.

You will work on multiple PIC tapeouts per year, develop test-chips for next-generation products, and push rapid iteration through the design-tapeout-Fab-validation loop, leveraging Cadence Virtuoso and related tools.

Qualifications

• Bachelor's or higher with 3–5+ years in silicon photonics or related field.
• Experience with photonics circuit modeling, layouts, and fabrication processes.
• Experience with photonic device layouts (passive and active) and GDS generation.
• Experience with lab measurements, data analysis, and automation (Matlab, LabVIEW, Python).

Responsibilities

• Own PIC product design cycle from simulation to layout and tapeout.
• Co-design opto-electronic chipsets with module teams to meet specs.
• Handle multiple PIC tapeouts per year and rapid iteration.
• Design and own test-chips to enable next-gen products.
• Drive design-tapeout-Fab-validation cycles.

Skills

Silicon photonics

Circuit modeling

GDS layout generation

Lab measurements

Data analysis

Python

Matlab

LabVIEW

Education

Bachelor's degree in a relevant field

Master's degree in a relevant field

PhD in a related field

Tools

Cadence Virtuoso

Cadence tools

HFSS

Matlab

LabVIEW

Python

Job description

Cisco Systems in California seeks a senior Silicon Photonics engineer to lead the full design cycle from photonic simulations to layout and tapeout, collaborating with EIC and module teams to deliver integrated opto-electronic chipsets.

You will work on multiple PIC tapeouts per year, develop test-chips for next-generation products, and push rapid iteration through the design-tapeout-Fab-validation loop, leveraging Cadence Virtuoso and related tools.