Silicon Photonics Optical Design Engineer

Cisco Systems, Inc; Allentown (Lehigh County); On-site; USD 138,000 - 198,000; Full time

Benefits offered by this job

Medical, dental, vision

401(k) matching

Paid parental leave

Disability coverage

Stock grants

Job summary

Cisco Systems, Inc. is seeking a seasoned Silicon Photonics engineer to drive full lifecycle PIC design—from simulation and layout to tapeout and post-fab validation. You will collaborate with EIC and module teams to deliver optimized photonic chipsets that meet system-level specs.

The role supports rapid iteration across multiple PICs per year, with opportunities to own test-chips for next‑generation products and to impact state-of-the-art silicon photonics in a global team.

Qualifications

• Bachelors + 5 years of related experience, or Masters + 3 years, or PhD + 0 years.
• Experience in Silicon Photonics circuit modeling, layouts/tapeouts, and fabrication process.
• Experience with photonic device layouts (passive and active) and GDS generation.
• Lab measurements, data analysis and automation using Matlab, LabVIEW, Python.

Responsibilities

• Ownership of PIC product design cycle from simulation to layout using Cadence Virtuoso to GDS tapeout.
• Co-design Opto-Electronic chipsets with module teams to meet system specs.
• Work during multiple PIC tapeouts per year to enable multiple products.
• Design and own small test-chips to enable next-gen products.
• Track design-tapeout-Fab-validation cycles with parallel PIC developments.

Skills

Silicon photonics

Circuit modeling

Layouts/tapeouts

GDS generation

Lab measurements

Data analysis

Automation

Cadence/Virtuoso

Matlab

Python

Education

Bachelor's +5 years

Master's +3 years

PhD +0 years

Tools

Cadence

Virtuoso

EDA tools

LabVIEW

MATLAB

Job description

Cisco Systems, Inc. is seeking a seasoned Silicon Photonics engineer to drive full lifecycle PIC design—from simulation and layout to tapeout and post-fab validation. You will collaborate with EIC and module teams to deliver optimized photonic chipsets that meet system-level specs.

The role supports rapid iteration across multiple PICs per year, with opportunities to own test-chips for next‑generation products and to impact state-of-the-art silicon photonics in a global team.