Optical Design Engineer - Silicon Photonics Innovator

Cisco Systems, Inc.; Carlsbad (CA); On-site; USD 138,000 - 198,000; Full time

Job summary

Cisco Systems, Inc. in California is seeking a Silicon Photonics engineer to own the PIC design cycle from simulation to tapeout and post-Fab validation.

You will collaborate with EIC and module teams to create optimized opto-electronic chipsets and lead multiple PIC tapeouts per year. You will also design small test-chips to advance next-generation products, driving rapid iteration through the tapeout-Fab cycle.

Qualifications

• Bachelor's degree with 5+ years of related experience, or Master's with 3+ years, or PhD with 0 years of related experience.
• Prior experience in Silicon Photonics circuit modeling, layouts/tapeouts, and fabrication process, including testing and validation.
• Prior experience in photonic device layouts both passive and active (GDS generation using appropriate EDA tools like Cadence, Virtuoso etc.)
• Prior experience with lab measurements, data analysis and automation using tools like Matlab, Labview, Python.

Responsibilities

• Own PIC product design cycle from simulation to layout using Cadence Virtuoso to final GDS tapeout to post-Fab validation.
• Work closely with EIC & module team to co-design highly optimized Opto-Electronic chipsets satisfying system-level specifications.
• In line with multiple PIC tapeouts a year, hitting ground running in first 6 months is expected to enable multiple products.
• Design and own small test-chips within a year or two to facilitate next-generation products.
• Many PIC tapeouts per year translates into parallel processing several PIC designs and tracking them through design-tapeout-Fab-validation cycle.

Skills

Silicon Photonics

Circuit modeling

Layouts/tapeouts

Lab measurements

Data analysis

Automation

Education

Bachelor's degree

Master's degree

PhD

Tools

Cadence Virtuoso

GDS generation

Cadence

Job description

Cisco Systems, Inc. in California is seeking a Silicon Photonics engineer to own the PIC design cycle from simulation to tapeout and post-Fab validation.

You will collaborate with EIC and module teams to create optimized opto-electronic chipsets and lead multiple PIC tapeouts per year. You will also design small test-chips to advance next-generation products, driving rapid iteration through the tapeout-Fab cycle.