Senior SiPh Design Engineer

Alpine Optoelectronics Inc.; San Francisco (CA); On-site; USD 140,000 - 240,000; Full time

Job summary

Alpine Optoelectronics Inc. is seeking a candidate to develop silicon photonics components and photonic integrated circuits (PIC) for next-generation data communications and 5G optical networks.

The role covers concept design, modeling, simulation, layout, and product testing, with responsibility for device-level layout efficiency and tape-out processes. Location noted as Fremont, California, with the position potentially ranging from junior to senior depending on qualification.

Qualifications

• PhD in Electrical Engineering, Physics, or related field with a focus on Integrated Photonics, with at least 2 years of direct Silicon Photonics device design experience.
• Skilled in programming for data analysis and layout design.
• Hands-on tape-out experience with at least one Silicon Photonics foundry and familiarity with its PDK.
• Proficiency in passive optical components such as edge/grating couplers, directional couplers, MMIs, and polarization splitters/rotators.
• Strong analytical and problem-solving abilities; excellent communication and teamwork skills.

Responsibilities

• Design, simulate, and layout passive or active photonic devices and PICs.
• Interact with silicon foundries and manage tape-out readiness.
• Test and characterize devices and PICs in the lab.

Skills

Data analysis

Layout design

Communication & teamwork

Education

PhD in Electrical Engineering or Physics with integrated photonics focus

Tools

Tape-out with silicon photonics foundry (PDK)

Photonic testing equipment

Job description

This position will be responsible for developing silicon photonics components, and photonic integrated circuits (PIC) to support next-generation data communications and 5G optical network applications. The responsibility spans from concept design, modeling & simulation to layout, and product testing. The candidate is expected to be responsible for product level layout and improve the efficiency of tape-out process.

The position could be a junior or senior role depending on the candidate’s qualification.

The scope of the responsibilities includes:

• Passive or active photonic device design, simulation, and layout using state-of-the-art modelling and layout tools.
• Interaction with the silicon foundry.
• Device and PIC test/characterization.

Qualifications and Skills

• PhD in Electrical Engineering, Physics, or a related field with a focus on Integrated Photonics, complemented by at least 2 years of direct experience in the design of Silicon Photonics devices.
• Skilled in programming for data analysis and layout design.
• Practical experience in tape-out process with at least one Silicon Photonics foundry, including familiarity with its PDK.
• Proficiency in passive optical components, such as edge couplers, grating couplers, directional couplers, MMIs, and polarization splitters and rotators.
• Hands-on experience with photonic testing equipment in a laboratory setting.
• Excellent analytical and problem-solving abilities.
• Strong communication skills and a proven ability to work both independently and as part of a team.

Work Location: Fremont, California