New Grad Silicon Engineer – ASIC/FPGA & RFIC

SpaceX; Palo Alto (CA); On-site; USD 135,000 - 210,000; Full time

Benefits offered by this job

Long-term incentives

Company stock

Discretionary bonuses

3 weeks paid vacation

10+ paid holidays

Comprehensive medical, vision and dent

Job summary

SpaceX is seeking a New Graduate Engineer for Silicon Engineering to join the Starlink program in Palo Alto, Irvine, or Redmond. The role covers ASIC/FPGA design, RFIC, DSP, and physical design across pre- to post-silicon stages.

Strong hands-on initiative and collaboration with cross-functional teams are essential for success. The position targets graduates in 2026/2027 with a BS/MS/PhD in engineering, mathematics, or physics and relevant ASIC/SOC/FPGA experience.

Qualifications

• Graduating with a bachelor’s, master’s or PhD in 2026 or 2027.
• Bachelor’s degree in an engineering discipline, mathematics or physics.
• Experience with ASIC, SOC, FPGA, RFIC, or MMIC.

Responsibilities

• Participate in all phases of ASIC/FPGA design and verification flows.
• Contribute towards design architecture, RTL implementation and/or verification, and emulation.
• Write embedded software using C/C++ and/or Python to bring-up and verify ASICs and FPGAs.

Skills

RTL design

SystemVerilog

Verilog

C/C++

Python

Education

Bachelor's degree in engineering, mathematics or physics

Graduating 2026 or 2027

Tools

ADS

Spectre

HFSS

Momentum

Job description

SpaceX is seeking a New Graduate Engineer for Silicon Engineering to join the Starlink program in Palo Alto, Irvine, or Redmond. The role covers ASIC/FPGA design, RFIC, DSP, and physical design across pre- to post-silicon stages.

Strong hands-on initiative and collaboration with cross-functional teams are essential for success. The position targets graduates in 2026/2027 with a BS/MS/PhD in engineering, mathematics, or physics and relevant ASIC/SOC/FPGA experience.