New Grad Silicon Engineer: ASIC/FPGA & DSP

InvestedintheMission; Redmond (WA); On-site; USD 125,000 - 200,000; Full time

Benefits offered by this job

Stock incentives and bonuses

Comprehensive medical, vision, dental

Job summary

SpaceX is seeking a NEW GRADUATE ENGINEER, SILICON ENGINEERING to help develop next generation silicon for Starlink. You will contribute across RF/Analog IC, RTL design, verification, physical design, and more using state-of-the-art tools and methodologies.

The role is full-time with locations in Palo Alto, Irvine, or Redmond. Ideal candidates are hands-on, eager to execute end-to-end design and verification with C/C++ and Python. Recent grads in 2026/2027 are encouraged to apply.

Qualifications

• Graduating with a bachelor’s degree, master’s degree or PhD in 2026 or 2027.
• Bachelor’s degree in an engineering discipline, mathematics or physics.
• Experience working with ASIC, SOC, FPGA, RFIC, or MMIC.

Responsibilities

• Participate in all phases of ASIC/FPGA design and verification flows.
• Contribute towards design architecture, RTL implementation and/or verification, and emulation.
• Bring-up and validate ASICs and FPGAs in the lab (write embedded software using C/C++ and/or Python).
• Hands-on self-starter who can execute the steps required to fully verify a complex digital design.
• Simulate and model RFIC systems and partition functions between hardware and software domains.
• Develop RTL designs using SystemVerilog and verify DSP blocks against MATLAB models.
• Perform synthesis and physical implementation steps and signoff checks.
• Participate in silicon tapeouts in advanced technology nodes for future Starlink SOCs.

Skills

ASIC/FPGA design

RFIC/Analog IC

DSP & RTL

SystemVerilog/VHDL/Verilog

C/C++ / Python

Python scripting

Digital design verification

Lab bring-up

Education

Bachelors in engineering / physics

Masters or PhD in related field

Tools

SystemVerilog

Verilog

VHDL

MATLAB

ADS / HFSS / Momentum

Job description

SpaceX is seeking a NEW GRADUATE ENGINEER, SILICON ENGINEERING to help develop next generation silicon for Starlink. You will contribute across RF/Analog IC, RTL design, verification, physical design, and more using state-of-the-art tools and methodologies.

The role is full-time with locations in Palo Alto, Irvine, or Redmond. Ideal candidates are hands-on, eager to execute end-to-end design and verification with C/C++ and Python. Recent grads in 2026/2027 are encouraged to apply.