New Grad Silicon Engineer: IC Design & Verification

Spacex

Redmond (WA)

On-site

USD 125,000 - 200,000

Full time

14 days+

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Benefits offered by this job

Stock options or incentives
Medical, vision and dental coverage
401(k) retirement plan
Paid time off and holidays

Job summary

SpaceX is seeking a NEW GRADUATE ENGINEER for silicon engineering to join the Starlink program and contribute from pre- through post-silicon across RF/Analog IC, RTL design, design verification, physical design and more in a hands-on role.

The position involves design, verification, and lab bring-up of ASICs/FPGA with embedded software in C/C++ or Python, plus opportunities to work across Silicon engineering disciplines in Redmond, Palo Alto or Irvine.

Qualifications

  • Graduating with a bachelor’s degree, master’s degree or PhD in 2026 or 2027.
  • Bachelor’s degree in an engineering discipline, mathematics or physics.
  • Experience working with ASIC, SOC, FPGA, RFIC, or MMIC.

Responsibilities

  • ASIC/FPGA Design & Verification: participate in all phases of ASIC/FPGA design and verification flows; contribute towards design architecture, RTL implementation and/or verification; bring-up and validate ASICs and FPGAs in the lab (write embedded software using C/C++ and/or Python).
  • RF/Analog IC Design: simulate and model RFIC systems; derive specifications; develop RF/microwave circuits; perform IC floor planning and layout.

Skills

ASIC/FPGA design
RF/Analog IC design
SystemVerilog / Verilog
C/C++ / Python
Digital signal processing
Computer architecture
RTL verification
Physical design

Education

Bachelor’s in engineering
Master’s or PhD in engineering/physics/math

Tools

ADS
Spectre
HFSS
Momentum

Job description

SpaceX is seeking a NEW GRADUATE ENGINEER for silicon engineering to join the Starlink program and contribute from pre- through post-silicon across RF/Analog IC, RTL design, design verification, physical design and more in a hands-on role.

The position involves design, verification, and lab bring-up of ASICs/FPGA with embedded software in C/C++ or Python, plus opportunities to work across Silicon engineering disciplines in Redmond, Palo Alto or Irvine.

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