New Grad ASIC Physical Design Engineer — Netlist & Timing Focus

NVIDIA Corporation; Santa Clara, Northern (CA, KY); Hybrid; USD 116,000 - 219,000; Full time

Job summary

NVIDIA seeks an ASIC Physical Design Engineer, Netlisting to join a dynamic, growing team in Santa Clara, CA. You will contribute to high-frequency and low-power CPUs, GPUs, and SoCs at block, cluster, or full-chip levels, focusing on netlist quality and verification processes.

The role requires advanced degrees or equivalent experience, strong knowledge of formal verification, RTL design, and scripting skills. Competitive salary and equity are offered.

Qualifications

• Master's or PhD degree in Electrical or Computer Engineering or equivalent experience.
• Shown knowledge in logic equivalence checking/Formal Verification required from RTL to tapeout with industry-standard tools.
• Understanding of hardware architecture and hands-on skills in RTL/logic design for timing closure.
• Experience in clock-domain-crossing checking, MTBF analysis, either with EDA tools or in-house tools.
• Background with logic synthesis at either block or full-chip level, at project execution and/or flow development.
• In-depth knowledge of industry standard EDA tools in related fields.
• Experience in programming and scripting languages, such as, Perl, TCL, Make, Python, etc.

Responsibilities

• Drive physical design of high-frequency and low-power CPUs, GPUs, SoCs at block/cluster/full-chip level.
• Focus on netlist-related tasks: equivalence checking, clock-domain crossing, MTBF analysis, and synthesis quality checks.
• Assist in ECO generation and implementation.

Skills

Logic equivalence checking

RTL/logic design

Clock-domain-crossing analysis

MTBF analysis

Programming/scripting (Perl, TCL, Make

Hardware architecture understanding

Formal verification

Education

Master's or PhD in Electrical or Computer Engineering

Tools

Synopsys

Cadence

Job description

NVIDIA seeks an ASIC Physical Design Engineer, Netlisting to join a dynamic, growing team in Santa Clara, CA. You will contribute to high-frequency and low-power CPUs, GPUs, and SoCs at block, cluster, or full-chip levels, focusing on netlist quality and verification processes.

The role requires advanced degrees or equivalent experience, strong knowledge of formal verification, RTL design, and scripting skills. Competitive salary and equity are offered.