New Grad ASIC Design Engineer: GPU/SoC Impact

NVIDIA Corporation; Santa Clara (CA); On-site; USD 100,000 - 189,750; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA is seeking an ASIC Design Engineer for a New College Grad class of 2026. Based in Santa Clara, CA, you will contribute to high-performance GPUs and SoCs, working through RTL design, verification and timing challenges.

You will collaborate with architects, verification, synthesis and back-end teams to deliver robust IPs such as schedulers, DMAs and controllers. The role emphasizes system-level understanding, micro-architecture, and hand-on RTL work with Verilog and scripting languages.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering or Computer Science.
• Experience in micro-architecture and RTL development (Verilog).
• Solid understanding of ASIC design flow including RTL design, verification, synthesis and timing.
• Exposure to Digital systems and VLSI design, Computer Architecture, and arithmetic.
• Strong interpersonal skills and teamwork.

Responsibilities

• Implement, document and deliver high performance RTL to meet design targets.
• Analyze architectural trade-offs based on features, performance and system limits.
• Craft micro-architecture, implement in RTL, and deliver fully verified designs.
• Collaborate with architects, verification, synthesis and back-end teams.
• Work on IPs such as GPU work scheduler, time distribution, interrupts and DMAs.

Skills

RTL development

Verilog

ASIC design flow

C/C++

Python

Education

Bachelor's degree in Electrical/Electrical and Computer Engineering or Computer Science

Tools

Simulation tools

Job description

NVIDIA is seeking an ASIC Design Engineer for a New College Grad class of 2026. Based in Santa Clara, CA, you will contribute to high-performance GPUs and SoCs, working through RTL design, verification and timing challenges.

You will collaborate with architects, verification, synthesis and back-end teams to deliver robust IPs such as schedulers, DMAs and controllers. The role emphasizes system-level understanding, micro-architecture, and hand-on RTL work with Verilog and scripting languages.