ASIC Physical Design & Netlisting Engineer | Equity Eligible

NVIDIA; United States; On-site; USD 116,000 - 190,000; Full time

Benefits offered by this job

Equity

Benefits package

Job summary

NVIDIA seeks a motivated ASIC Physical Design Engineer focusing on Netlisting to join our dynamic team. You'll drive high-frequency, low-power block/full-chip design, emphasize netlist checks, and support ECO generation and implementation.

Required are advanced degrees in Electrical/Computer Engineering, expertise in equivalence checking and formal verification, and strong RTL/timing closure experience with industry tools (Synopsys/Cadence). Proficiency in scripting (Python) is valued.

Qualifications

• Master's or PhD in Electrical or Computer Engineering or equivalent.
• Knowledge in logic equivalence checking/Formal Verification from RTL to tapeout.
• Understanding of hardware architecture; RTL/logic design for timing closure.
• Experience in clock-domain-crossing checking; MTBF analysis with EDA tools.
• Background with logic synthesis at block or full-chip level; project execution/flow development.
• Knowledge of standard EDA tools in related fields.
• Experience in programming/scripting languages (Perl, TCL, Make, Python).

Responsibilities

• Drive physical design of high-frequency and low-power CPUs, GPUs, SoCs at block, cluster, or full-chip level, focusing on netlist-related checks.
• Help in ECO generation and implementation.

Skills

Netlisting

Equivalence checking

Formal verification

RTL design

Timing closure

Clock domain crossing

Scripting: Python

Education

Master's or PhD in Electrical or Computer Engineering

Tools

Synopsys

Cadence

In-house tools

Job description

NVIDIA seeks a motivated ASIC Physical Design Engineer focusing on Netlisting to join our dynamic team. You'll drive high-frequency, low-power block/full-chip design, emphasize netlist checks, and support ECO generation and implementation.

Required are advanced degrees in Electrical/Computer Engineering, expertise in equivalence checking and formal verification, and strong RTL/timing closure experience with industry tools (Synopsys/Cadence). Proficiency in scripting (Python) is valued.