Entry-Level CPU ASIC Design Engineer — Equity

NVIDIA Corporation; Santa Clara (CA); On-site; USD 100,000 - 189,750; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA Corporation is seeking a new college graduate for an ASIC design engineer role in Santa Clara. You will join the CPU logic design team to create high-performance, power-efficient chip units, with RTL coding, synthesis, timing analysis and lab debugging.

The role requires Verilog expertise, strong computer architecture knowledge and collaboration with verification and implementation teams. Equity and benefits accompany the base compensation.

Qualifications

• BS or MS degree in Electrical Engineering, Computer Engineering or Computer Science (or equivalent).
• Experience in processor or related high-performance semiconductor designs is preferred.
• Proficiency in Verilog and ASIC design flow, including RTL, synthesis, timing analysis, and lab debugging.

Responsibilities

• Own and deliver a unit on the chip within the CPU core team.
• Write readable RTL for high performance and low power designs; perform synthesis and timing closure.
• Collaborate with verification to ensure correctness of the unit.
• Assist timing closure of larger blocks and support implementation goals.

Skills

Verilog

RTL design

ASIC design

Computer architecture

Cache coherency

Timing closure

Synthesis

DFT

Lab debugging

High-performance design

Education

BS/MS in Electrical Engineering or Computer Engineering or Computer Science

Tools

Synthesis tools

DFT tools

EDA tools

Floorplanning

Job description

NVIDIA Corporation is seeking a new college graduate for an ASIC design engineer role in Santa Clara. You will join the CPU logic design team to create high-performance, power-efficient chip units, with RTL coding, synthesis, timing analysis and lab debugging.

The role requires Verilog expertise, strong computer architecture knowledge and collaboration with verification and implementation teams. Equity and benefits accompany the base compensation.