ASIC Physical Design Engineer - New Grad 2026 (Equity)

NVIDIA Gruppe; Santa Clara (CA); On-site; USD 116,000 - 219,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA in California is seeking a candidate for the physical design of high-frequency CPUs, GPUs and SoCs, focusing on netlist tasks, equivalence checking, clock-domain crossing and MTBF analysis.

Requirements include a Master’s or PhD in Electrical or Computer Engineering, hands-on RTL/logic design for timing closure, experience with EDA tools (Synopsys or Cadence), and scripting in Perl, TCL, Make or Python. Applications accepted until May 11, 2026.

Qualifications

• Master’s or PhD in Electrical or Computer Engineering (or equivalent).
• Experience in logic equivalence checking/formal verification from RTL to tapeout with industry tools.
• Understanding of hardware architecture and RTL/logic design for timing closure.
• Experience in clock-domain-crossing checking, MTBF analysis with EDA tools or in-house tools.
• Background with logic synthesis at block or full-chip level, project execution or flow development.
• Familiarity with industry standard EDA tools.
• Experience in programming/scripting languages such as Perl, TCL, Make, Python, etc.

Responsibilities

• Drive physical design of high-frequency and low-power CPUs, GPUs, SoCs at block/cluster/full-chip level with focus on netlist-related checks and ECO generation.
• Help in ECO generation and implementation.

Skills

Logic equivalence checking

Formal verification

RTL/logic design

Clock-domain-crossing

MTBF analysis

Logic synthesis

Programming/scripting

Education

Master's degree in Electrical or Computer Engineering

PhD in Electrical or Computer Engineering

Tools

Synopsys

Cadence

Job description

NVIDIA in California is seeking a candidate for the physical design of high-frequency CPUs, GPUs and SoCs, focusing on netlist tasks, equivalence checking, clock-domain crossing and MTBF analysis.

Requirements include a Master’s or PhD in Electrical or Computer Engineering, hands-on RTL/logic design for timing closure, experience with EDA tools (Synopsys or Cadence), and scripting in Perl, TCL, Make or Python. Applications accepted until May 11, 2026.