Mixed-Signal Verification Engineer for RF/SoC

Eastridge; San Jose (CA); On-site; USD 129,000 - 214,000; Part time

Job summary

Eastridge Workforce Solutions seeks a Mixed Signal Verification Engineer in San Jose, CA, to design AMS/DMS testbenches for wireless RF and high-speed PHY designs. The role emphasizes analog model validation and silicon bring-up support.

Ideal candidates have 3+ years in verification, strong Verilog/SystemVerilog and RNM modeling experience, and proficiency with UVM-based verification and waveform debugging.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field.
• 3+ years of relevant verification or mixed-signal engineering experience.
• Strong understanding of digital VLSI simulation flows.
• Strong knowledge of mixed-mode and analog simulation flows.
• Hands-on experience with Verilog/SystemVerilog.
• Experience developing RNM/real-number models.
• Experience with UVM-based digital verification and waveform debugging.
• Strong analytical, troubleshooting, and communication skills.
• Ability to work effectively within cross-functional engineering teams.

Responsibilities

• Create and maintain AMS/DMS testbenches for wireless RF and high-speed PHY designs.
• Partner with RF and Analog Design Engineers to develop and validate analog circuit models.
• Develop Real Number Models (RNM) for mixed-signal verification.
• Perform digital and mixed-mode simulations and debug verification failures.
• Develop and execute verification environments using SystemVerilog and UVM.
• Analyze simulation results and perform waveform debugging.
• Support silicon bring-up, validation, and commercialization activities.
• Collaborate with cross-functional design, verification, and validation teams.

Skills

AMS/DMS testbenches

Analog behavioral models

RNM/real-number models

SystemVerilog

UVM-based verification

Waveform debugging

Cross-functional collaboration

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field

Tools

Verilog/SystemVerilog

UVM

RNM tools

Job description

Eastridge Workforce Solutions seeks a Mixed Signal Verification Engineer in San Jose, CA, to design AMS/DMS testbenches for wireless RF and high-speed PHY designs. The role emphasizes analog model validation and silicon bring-up support.

Ideal candidates have 3+ years in verification, strong Verilog/SystemVerilog and RNM modeling experience, and proficiency with UVM-based verification and waveform debugging.