Mixed-Signal Verification Engineer — Analog/RF Modeling

Apple Inc.; Sunnyvale (CA); On-site; USD 140,000 - 190,000; Full time

Job summary

Apple Inc. in Sunnyvale seeks a Design Verification Engineer to verify functionality and performance of Apple’s premier SoCs. The role focuses on RNM/SystemVerilog behavioral modeling for analog/RF blocks inside a large SoC, with self-checking models and AMS environment setup alongside analog designers.

You will own modeling tasks, develop assertions, and ensure specs are met while collaborating across the hardware team to deliver high-quality verification results.

Qualifications

• Bachelor's degree in engineering or related field.
• Strong fundamentals in analog/RF circuit theory/topologies.
• Experience with RNM coding in SystemVerilog.

Responsibilities

• Develop RNM RF/Analog models in SystemVerilog.
• Create models with self-checking techniques.
• Assess required model accuracy for verification goals.
• Develop assertions to ensure analog/digital specs are met and define digital verification criteria.
• Collaborate with analog designers to set up AMS simulation environments.
• Debug complex chip digital-on-top testbenches and identify root causes of failures.

Skills

RNM/SystemVerilog

Analog/RF theory

AMS verification

Digital verification

Education

Bachelor's degree

MS (preferred)

Tools

Cadence mixed signal verification environment

Job description

Apple Inc. in Sunnyvale seeks a Design Verification Engineer to verify functionality and performance of Apple’s premier SoCs. The role focuses on RNM/SystemVerilog behavioral modeling for analog/RF blocks inside a large SoC, with self-checking models and AMS environment setup alongside analog designers.

You will own modeling tasks, develop assertions, and ensure specs are met while collaborating across the hardware team to deliver high-quality verification results.