Mixed-Signal Design Architect for HBM AI Memory

Micron Technology, Inc.; Folsom (CA); On-site; USD 146,000 - 297,000; Full time

Job summary

Micron Technology, Inc. in Folsom, California, is seeking a Mixed-signal Design Architect for HBM architecture.

You will design and optimize analog/mixed-signal circuits, analyze power delivery, and prototype interfaces for 3D-stacked memory products, collaborating with architecture and design teams. The role requires strong transistor-level simulation experience (FineSim, HSPICE) and the ability to assess architectural tradeoffs.

Qualifications

• Experience with analog and/or mixed-signal design, including simulation and floorplanning.
• Experience with transistor-level simulation (e.g., FineSim, HSPICE) including corner analysis.
• Ability to analyze architecture tradeoffs and use findings to develop specifications.
• Experience with power delivery analysis, tradeoffs, constraints, and challenges.

Responsibilities

• Design, optimize, and simulate critical analog and/or mixed-signal circuits.
• Architect and design power delivery for high-performance, stacked memories.
• Analyze, specify, and prototype on-/off-chip interfaces.
• Perform timing, area, power, and complexity analysis for high-performance, low-power circuits.
• Define architectures for improved thermal management.
• Conduct pathfinding activities for future-generation stacked-memory products.
• Compose and maintain clear architecture documentation.

Skills

Analog/mixed-signal design

Transistor-level simulation

Architecture tradeoffs analysis

Power delivery analysis

Thermal management concepts

Education

Masters or PhD in Computer Science, Computer Engineering, Electrical Engineering, or equivalent experience

Tools

FineSim

HSPICE

Verilog

Python

Perl

Job description

Micron Technology, Inc. in Folsom, California, is seeking a Mixed-signal Design Architect for HBM architecture.

You will design and optimize analog/mixed-signal circuits, analyze power delivery, and prototype interfaces for 3D-stacked memory products, collaborating with architecture and design teams. The role requires strong transistor-level simulation experience (FineSim, HSPICE) and the ability to assess architectural tradeoffs.