Mixed‑Signal Design Architect for Next‑Gen HBM Systems

Micron Technology, Inc; Folsom (CA); Sur place; USD 146 000 - 297 000; Plein temps

Résumé du poste

Micron Technology, Inc. seeks a Senior/Principal Engineer or Senior Staff to design, simulate, and optimize 3D-stacked, high-performance memories for AI workloads.

You will lead analog/mixed-signal circuit efforts, power delivery architectures, and interface specifications in collaboration with architecture teams. Responsibilities include defining architectures, evaluating thermal and power delivery, and prototyping on-/off-chip interfaces while maintaining clear documentation and advancing

Qualifications

• Experience with analog and/or mixed-signal design, including simulation and floorplanning.
• Experience with transistor-level simulation (e.g., FineSim, HSPICE) including corner analysis.
• Ability to analyze architecture tradeoffs and use findings to develop specifications.
• Experience with power delivery analysis, tradeoffs, constraints, and challenges.

Responsabilités

• Design, optimize, and simulate critical analog and/or mixed-signal circuits.
• Architect and design power delivery for high-performance, stacked memories.
• Analyze, specify, and prototype on-/off-chip interfaces.
• Perform timing, area, power, and complexity analysis for high-performance, low-power circuits.
• Define architectures for improved thermal management.
• Conduct pathfinding activities for future-generation stacked-memory products.
• Compose and maintain clear architecture documentation.

Connaissances

Analog/Mixed-signal design

Architecture tradeoffs

Power delivery analysis

Transistor-level simulation

Circuit timing/area/power analysis

Thermal management concepts

Scripting (Python/Perl)

Verilog (HDL)

Formation

Masters/PhD in EE/CS or related field

Outils

FineSim

HSPICE

Verilog

Python

Perl

Description du poste

Micron Technology, Inc. seeks a Senior/Principal Engineer or Senior Staff to design, simulate, and optimize 3D-stacked, high-performance memories for AI workloads.

You will lead analog/mixed-signal circuit efforts, power delivery architectures, and interface specifications in collaboration with architecture teams. Responsibilities include defining architectures, evaluating thermal and power delivery, and prototyping on-/off-chip interfaces while maintaining clear documentation and advancing