Senior CPU Physical Design & Integration Engineer

Apple Inc.; California (MO); On-site; USD 150,000 - 278,000; Full time

Job summary

Apple Inc. in Santa Clara, California is seeking a CPU Physical Design and Integration Engineer to lead physical design, integration, and verification for high-performance CPU development. You will own floorplanning, PnR, and IP integration across the design cycle.

The role requires a BS with 3+ years of experience, scripting in Perl/Tcl, and knowledge of physical design tools. Collaboration with CAD teams and SOC teams is essential for on-time tapeouts and robust IP delivery.

Qualifications

• Minimum BS and 3+ years of relevant industry experience.
• Experience with place and route and physical verification.
• Experience with a scripting language such as Perl or Tcl.

Responsibilities

• Full chip floorplan, area optimizations, block partitioning and pin placements.
• Own chip level place and route (PnR), final CPU layout database construction, and verification (PDV).
• Evaluate route ability, power grid and technology bring up.
• Drive custom layout integration and IPs for CPU.
• Work with the Implementation/CAD teams during the entire chip design cycle to drive signoff closure for tapeout.
• Work with the SOC team to meet IP technical and delivery requirements.
• Participate in establishing CAD and physical design methodologies.
• Participate in flow development for chip integration and analysis.
• Scripting to automate tasks and improve debug efficiency.

Skills

Place & Route

Physical Verification

Perl/Tcl scripting

Education

Bachelor's degree

Tools

PDV tools

DRC/LVS verification tools

Job description

Apple Inc. in Santa Clara, California is seeking a CPU Physical Design and Integration Engineer to lead physical design, integration, and verification for high-performance CPU development. You will own floorplanning, PnR, and IP integration across the design cycle.

The role requires a BS with 3+ years of experience, scripting in Perl/Tcl, and knowledge of physical design tools. Collaboration with CAD teams and SOC teams is essential for on-time tapeouts and robust IP delivery.