Microarchitect

Conductor; Austin, Boston, San Francisco (TX, MA, CA); Hybrid; USD 180,000 - 240,000; Full time

Job summary

Conductor is seeking microarchitects to own key blocks in the A-0 and A-1 systems. You will translate specifications into implementable RTL and collaborate with the PD teams to turn it into silicon.

You will work with architects to shape microarchitecture across blocks and ensure integration into the broader system. Ideal candidates have demonstrated ownership of microarchitecture in tapeouts, deep understanding of PPA impact, and experience with system‑level design and block integration.

Qualifications

• Ideal candidates will have ownership of microarchitecture for at least one block across advanced node tapeouts.
• Deep understanding of how microarchitecture affects PPA and levers to improve it.
• Understanding of system level architecture and its impact on microarchitecture.
• Understanding of integrating blocks into a broader system.
• Experience with AI chip microarchitecture, especially matrix multiplication engines (nice to have).
• Knowledge of matrix multiplication engine numerics and effects on microarchitecture (nice to have).
• Experience with 5nm and below nodes (nice to have).
• Experience with physical design processes at 7nm and below nodes (nice to have).

Responsibilities

• Own key microarchitectural blocks in the A-0 and A-1 systems.
• Translate specifications into implementable RTL.
• Collaborate with PD teams to turn RTL into silicon.

Skills

Microarchitecture ownership

PPA impact understanding

System-level architecture

Block integration into system

Job description

We’re looking for microarchitects to own key blocks in the A-0 and A-1 systems. You will work alongside the architects to translate specifications into implementable RTL and then work with the PD teams to turn it into silicon.

Ideal Background:

Ideal candidates will have:

• Experience owning the microarchitecture of at least one block in multiple advanced node tapeouts
• Deep understanding of impact of microarchitecture upon PPA, and levers available to improve PPA
• Understanding of system level architecture and the impact of microarchitecture upon system architecture
• Understanding of integration of blocks into broader system

Nice to Have:

• Experience with microarchitecture of AI chip blocks, especially matrix multiplication engines
• Knowledge of matrix multiplication engine numerics and effects upon microarchitecture
• Experience with microarchitecture at 5nm and below nodes
• Experience with physical design process at 7nm and below nodes