Physical Design Engineer

Conductor; Austin, Boston, San Francisco (TX, MA, CA); Hybrid; USD 130,000 - 170,000; Full time

Job summary

Conductor, based in Austin, TX, is seeking physical design engineers to lead the physical design process for our A-0 and A-1 system dies. You will decide what to do in-house and what to outsource, then manage the outsourced flow and integrate it with the in-house flow and effort.

Ideal candidates have hands-on experience with tapeouts, RTL PPA considerations, and experience with in-house and outsourced flows.

Qualifications

• Hands-on experience with the physical design process for at least one block in multiple advanced node tapeouts.
• Ability to understand PPA limiters from RTL and coordinate with microarchitects to improve RTL.
• Experience with in-house and outsourced physical design flows.

Responsibilities

• Lead and manage the physical design process for multiple dies in our A-0 and A-1 systems.
• Decide what design work to keep in-house vs. outsource and drive integration with in-house flow.
• Collaborate with RTL and microarchitecture teams to optimize PPA and overall performance.

Skills

Physical design

RTL coordination

In-house/outsourced flows

Job description

We’re looking for physical design engineers to help manage and execute the physical design process for the various dies that comprise our A-0 and A-1 systems. This will involve deciding what to do in-house and outsource, and then managing the outsourced process and integrating it with the in-house flow and effort.

Ideal Candidates:

Ideal candidates will have:

• Hands-on experience with the physical design process for at least one block in multiple advanced node tapeouts
• Ability to understand what PPA limiters are from RTL and coordinate with microarchitects to change the RTL to improve/fix them
• Experience both with in-house and outsourced physical design flows

Nice to Have:

• Experience with physical design process for multi-die/multi-chiplet/MCM designs
• Experience with physical design process for reticle-max or near reticle max designs
• Experience with very high power density chips
• Experience with the physical design process for AI chips
• Experience with the physical design process of analog and mixed signal blocks and macros