ASIC Design Engineer - Multi-Die & AI Chips

Conductor; Austin, Boston, San Francisco (TX, MA, CA); Hybrid; USD 130,000 - 210,000; Full time

Job summary

Conductor is seeking ASIC design engineers to contribute to and own blocks in the A-0 and A-1 wafer products, spanning XPU, memory chiplet and other dies on the wafer.

You will drive design ownership, optimize PPA, and iterate rapidly across multiple advanced node tapeouts, applying creative methodologies to accelerate development and improve performance.

Strong candidates will demonstrate hands-on tapeouts and end-to-end block ownership across complex die architectures.

Qualifications

• Hands-on tapeouts on multiple advanced nodes.
• Led the ASIC design portion of at least one block.
• Understands PPA and stack levers.
• Creative methodology for fast iterations.

Skills

Advanced node tapeouts

ASIC ownership

PPA optimization

Fast design iterations

Job description

Conductor is seeking ASIC design engineers to contribute to and own blocks in the A-0 and A-1 wafer products, spanning XPU, memory chiplet and other dies on the wafer.

You will drive design ownership, optimize PPA, and iterate rapidly across multiple advanced node tapeouts, applying creative methodologies to accelerate development and improve performance.

Strong candidates will demonstrate hands-on tapeouts and end-to-end block ownership across complex die architectures.