SoC Architect

Conductor; Austin, Boston, San Francisco (TX, MA, CA); Hybrid; USD 180,000 - 280,000; Full time

Job summary

Conductor is seeking SoC architects to own the detailed SoC-level architecture of dies on the A-0 and A-1 wafer-scale systems. You will work with the architecture and ASIC design teams to create implementable specs and drive the execution of said implementations.

Ideal candidates will have ownership of specs for at least one SoC/die, deep understanding of architecture, microarchitecture and physical design, and the ability to coordinate with multiple groups to drive SoC implementation.

Qualifications

• Ownership of specs and drive implementation for at least one SoC/die.
• Deep understanding of architecture, microarchitecture and physical design and the ability to coordinate with various groups to drive implementation of SoCs.
• Understanding of SoC interactions with packages, memory subsystems and IO, and ability to work with teams who are responsible for said interacting blocks.

Responsibilities

• Own the detailed SoC-level architecture of dies on the A-0 and A-1 wafer-scale systems.
• Collaborate with architecture and ASIC design teams to create implementable specs and drive execution.
• Coordinate with multiple groups to drive reliable, high-quality silicon delivery.

Skills

SoC architecture ownership

Full SoC/die ownership

Microarchitecture

Physical design coordination

Package/memory/IO interactions

Job description

We’re looking for SoC architects to own the detailed SoC-level architecture of dies on the A-0 and A-1 wafer-scale systems. You will work with the architecture and ASIC design teams to create implementable specs and drive the execution of said implementations.

Ideal Background:

An ideal candidate will have:

• Experience with full ownership of the specs and drove implementation for at least one SoC/die
• A deep understanding of the process of architecture, microarchitecture and physical design and the ability to coordinate with various groups to drive implementation of SoCs
• Understanding of SoC interactions with packages, memory subsystems and IO, and ability to work with teams who are responsible for said interacting blocks

Nice to Have:

• Experience with multi-die/multi-chiplet/MCM designs
• Experience with reticle-max/large-die SoC architecture
• Understanding of levers available for improving PPA
• Track record of very high speed A0 silicon delivery