ASIC Design Engineer

Conductor; Austin, Boston, San Francisco (TX, MA, CA); Hybrid; USD 130,000 - 210,000; Full time

Job summary

Conductor is seeking ASIC design engineers to contribute to and own blocks in the A-0 and A-1 wafer products, spanning XPU, memory chiplet and other dies on the wafer.

You will drive design ownership, optimize PPA, and iterate rapidly across multiple advanced node tapeouts, applying creative methodologies to accelerate development and improve performance.

Strong candidates will demonstrate hands-on tapeouts and end-to-end block ownership across complex die architectures.

Qualifications

• Hands-on tapeouts on multiple advanced nodes.
• Led the ASIC design portion of at least one block.
• Understands PPA and stack levers.
• Creative methodology for fast iterations.

Skills

Advanced node tapeouts

ASIC ownership

PPA optimization

Fast design iterations

Job description

We’re looking for ASIC design engineers to contribute to and own blocks in the development of the A-0 and A-1 wafer products, across both the XPU, memory chiplet and other dies on the wafer.

Ideal Background:

• Hands-on experience with multiple advanced node tapeouts
• Ownership of ASIC design portion of at least one block in multiple advanced node tapeouts
• Understanding of PPA improvement and what levers exist for each level of the stack
• Ability to think creatively about methodology for fast design iterations

Nice to Have:

• Hands-on experience with ASIC design process for large die (ideally reticle max) chips
• Hands-on experience with ASIC design process for AI chips
• Hands-on experience with multi-die/multi-chiplet/MCM designs