Memory Subsystem Engineer: Customer Debug & Design Lead

AMD; San Jose (CA); On-site; USD 190,000 - 260,000; Full time

Benefits offered by this job

AMD benefits at a glance

Job summary

AMD in San Jose seeks a memory systems engineer to drive customer success across DDR/LPDDR memory subsystems and the memory controller portfolio. You will be the technical contact for escalated issues, root-cause failures on real systems, and guide design-in through production support.

You will author customer-facing docs, review architectures for next-generation silicon, and contribute to program decisions across IP, firmware, tools, and signal integrity teams, collaborating across time zones.

Qualifications

• Experience with memory subsystems across multiple DRAM generations.
• Fluency in JEDEC DDR/LPDDR specifications and module variants.
• Proven ability to author customer-facing documentation and present findings.

Responsibilities

• Own escalated memory customer support from design-in to production.
• Be the authority on DDR/LPDDR and Network-on-Chip interconnects and budgeting.
• Author customer-facing documentation and publish resolutions.
• Review memory/NoC architecture and validate RAS features.
• Perform memory SI/PI and timing measurements with PCB routing knowledge.
• Translate system challenges into product/roadmap decisions across multiple teams.

Skills

Memory subsystems

DDR/LPDDR knowledge

Root cause analysis

Hardware debugging

Technical writing

Customer collaboration

C programming

NoC interconnects

Tools

IBIS/IBIS-AMI models

Oscilloscopes

Logic analyzers

BERTs

PCB layout knowledge

Job description

AMD in San Jose seeks a memory systems engineer to drive customer success across DDR/LPDDR memory subsystems and the memory controller portfolio. You will be the technical contact for escalated issues, root-cause failures on real systems, and guide design-in through production support.

You will author customer-facing docs, review architectures for next-generation silicon, and contribute to program decisions across IP, firmware, tools, and signal integrity teams, collaborating across time zones.