Principal Memory Subsystem Architect

AMD; Georgia; Hybrid; USD 180,000 - 240,000; Full time

Job summary

AMD's Memory Standards Architecture team seeks a LPDDR and DRAM-Buffer Standards Architect to own the architecture strategy across generations and devices. The role requires deep LPDDR and DDR knowledge, leadership across internal teams, and influence with external partners to shape the memory ecosystem.

You will define roadmaps, represent AMD in JEDEC, and align DRAM vendors, suppliers, and platforms to deliver robust, power-aware, and interoperable solutions for client, server, and embedded

Qualifications

• Deep LPDDR and DDR knowledge with architecture experience.
• Experience with DRAM-bit architectures, buffers, and memory systems.
• Ability to influence across internal teams and external partners.

Responsibilities

• Own AMD’s LPDDR and DRAM-buffer architecture strategy across business units and product generations.
• Lead AMD technical positions for LPDDR devices and advanced DRAM buffers.
• Advance AMD positions in JEDEC through proposals, ballots, negotiations.
• Align AMD with DRAM vendors, buffer suppliers, and the memory ecosystem.
• Consolidate product, platform, design, validation, firmware, and system needs into unified AMD positions.
• Strategy and roadmap: Define multi-generation LPDDR and DRAM-buffer strategy.
• Standards leadership: Represent AMD in JEDEC and drive consensus.
• Device and buffer architecture: Define requirements for LPDDR devices and buffers.
• System integration: Coordinate DRAM and buffer architectures with controller, PHY, SoC, package, module, board, firmware, validation, and platform requirements.
• Implementation specifications: Deliver architecture, SPD, configuration, firmware, power, security requirements.
• Ecosystem readiness: Align DRAM vendors and suppliers on roadmaps and interoperability.
• Lead cross-functional architecture workgroups and provide reusable solutions and guidance.

Skills

LPDDR architecture

DRAM-buffer architectures

JEDEC standards

cross-functional leadership

system-level architecture

power and performance tradeoffs

collaboration with vendors

Education

Bachelor's degree in EE/CE/CS

Master's degree or PhD preferred

Job description

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believetechnology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMDis shapingthefuture.

Whetheryou’redesigning next-gen processors, enabling AI breakthroughs, orbringing leading edge products to market, every role at AMD contributes to something bigger— technologythat moves the world forward.Join us and, together, we’ll advance your career.

THE ROLE:

The Memory Standards Architecture team seeks an LPDDR and DRAM Buffer Standards Architect to own AMD’s architecture strategy for low-power DRAM and advanced memory-buffer technologies.

This architect will define AMD’s multi-generation LPDDR and DRAM-buffer roadmap; lead technical positions for LPDDR devices, DDR6 registered clock drivers, LPDDR6 in-package buffers, and future buffer architectures; and represent AMD in JEDEC and the broader memory ecosystem.

• Own AMD’s LPDDR and DRAM-buffer architecture strategy across business units and product generations.
• Lead AMD technical positions and serve as the company-wide authority for LPDDR devices and advanced DRAM buffers.
• Advance AMD positions in JEDEC through proposals, ballots, negotiations, partnerships, and consensus building.
• Align AMD business units, DRAM vendors, buffer suppliers, and the broader memory-component ecosystem.

Serving Client, Server, Embedded, S3, and other adopting businesses, the architect will consolidate product, platform, design, validation, firmware, package, and system needs into unified AMD positions, supplier requirements, implementation specifications, and platform guidance.

THE PERSON:

You are a recognized memory-technology expert who can move effectively between detailed device and interface architecture, system-level tradeoffs, industry standards, and executive decision-making. You bring deep LPDDR and DDR knowledge, sound architectural judgment, and a demonstrated ability to align internal teams and external partners around technically rigorous, implementable positions.You communicate complex decisions clearly, resolve competing technical priorities, and build consensus while considering performance, power, reliability, cost, interoperability, qualification, and schedule constraints. You are comfortable leading through influence across organizational and company boundaries.

KEY RESPONSIBILITIES:

• Strategy and roadmap: Define AMD’s multi-generation LPDDR and DRAM-buffer strategy, adoption plans, priorities, ownership, risks, and business-unit decisions across Client, Server, Embedded, S3, and other adopting organizations.
• Standards leadership: Represent AMD in JEDEC and related forums through technical proposals, ballots, negotiations, partnerships, and consensus building; maintain approved AMD positions and drive closure of standards dependencies.
• Device and buffer architecture: Define requirements for LPDDR devices, DDR6 registered clock drivers, LPDDR6 in-package buffers, future buffer architectures, and supporting components, including partitioning, topology, interfaces, protocols, clocking, performance, power, training, telemetry, reliability, security, test, error handling, recovery, and interoperability.
• System integration: Coordinate DRAM and buffer behavior with controller, PHY, SoC, package, module, board, firmware, validation, and platform requirements; guide tradeoffs among discrete, module-level, in-package, die-integrated, DRAM-integrated, and host-side implementations.
• Implementation specifications: Deliver architecture, SPD, configuration, authentication, attestation, firmware, power, thermal, packaging, platform, compliance, margining, characterization, robustness, and fault-handling requirements and guidance.
• Ecosystem readiness: Align DRAM vendors and suppliers of buffers, PMICs, regulators, hubs, connectors, and related technologies on roadmaps, qualification plans, interoperability, readiness milestones, and adoption risks.
• Cross-functional execution: Serve as the company-wide architecture authority, lead internal workgroups, resolve technical tradeoffs, document decisions and ownership, and provide business-unit teams with specifications, reusable solutions, implementation guidance, issue resolution, and launch-readiness support.

KEY RESPONSIBILITIES:

• Own AMD’s multi-generation LPDDR and DRAM-buffer architecture strategy, including adoption plans, priorities, risks, ownership, and business-unit decisions, and serve as the company-wide technical authority for LPDDR devices, registered clock drivers, and advanced DRAM-buffer technologies.
• Develop and maintain AMD technical positions for JEDEC and related standards organizations, advancing standards work through proposals, ballots, technical negotiations, objection resolution, partnerships, and consensus building.
• Define architectural requirements for LPDDR devices, DDR6 registered clock drivers, LPDDR6 in-package buffers, future buffer architectures, and supporting components.
• Establish requirements covering partitioning, topology, interfaces, protocols, command and data behavior, clocking, training, performance, power, telemetry, reliability, security, test, error handling, recovery, and interoperability.
• Coordinate DRAM and buffer architectures with controller, PHY, SoC, package, module, board, firmware, validation, and platform requirements, evaluating tradeoffs among discrete, module-level, in-package, die-integrated, DRAM-integrated, and host-side implementations.
• Deliver implementation requirements and guidance for architecture, SPD, configuration, firmware, authentication, attestation, power, thermal design, packaging, compliance, margining, characterization, robustness, and fault handling.
• Align DRAM vendors and suppliers of buffers, PMICs, regulators, hubs, connectors, and related technologies on roadmaps, qualification plans, interoperability, readiness milestones, and adoption risks.
• Lead cross-functional architecture workgroups, document decisions and ownership, resolve technical tradeoffs, drive closure of standards and implementation dependencies, and provide adopting teams with reusable solutions, specifications, implementation guidance, issue resolution, and launch-readiness support.

Education and Experience:

Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field required; master’s degree or PhD preferred.

This role is not eligible for visa sponsorship.

#LI-TB1

#LI-Hybrid

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.