Memory Subsystem Verification Engineer (UVM/Verilog)

Socket.dev; Santa Clara (CA); On-site; USD 153,000 - 230,000; Full time

Job summary

Qualcomm Technologies, Inc. is seeking a motivated Design Verification Engineer to join its memory subsystem verification team.

You will develop verification strategies for memory controllers, DDR/LPDDR/HBM interfaces, and PHY-related logic, and execute simulations using UVM-based testbenches. The role involves creating assertions, driving functional and code coverage closure, and collaborating with RTL, architecture, and modeling teams to ensure verifiability and design correctness across

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
• 3–10 years of experience in ASIC, SoC, IP, or subsystem design verification.
• Strong hands-on experience with Verilog, SystemVerilog, UVM, SystemVerilog Assertions.

Responsibilities

• Develop verification strategies, test plans, and coverage plans for complex RTL designs.
• Build, enhance, and maintain reusable SystemVerilog/UVM and formal verification environments.
• Develop and maintain UVM components, including sequences, drivers, monitors, scoreboards, agents, environments, and test configurations.
• Create and execute constrained-random, directed, error-injection, and corner-case tests.
• Write and maintain SystemVerilog Assertions for protocol, interface, timing, and functional verification.
• Verify memory-controller, PHY-interface, and memory-subsystem functionality across multiple operating modes.
• Analyze simulation failures using waveform viewers, simulation logs, transaction databases, and other debug tools.

Skills

Verilog

SystemVerilog

UVM

SystemVerilog Assertions

Education

Bachelor's degree

Master's degree

PhD

Job description

Qualcomm Technologies, Inc. is seeking a motivated Design Verification Engineer to join its memory subsystem verification team.

You will develop verification strategies for memory controllers, DDR/LPDDR/HBM interfaces, and PHY-related logic, and execute simulations using UVM-based testbenches. The role involves creating assertions, driving functional and code coverage closure, and collaborating with RTL, architecture, and modeling teams to ensure verifiability and design correctness across