Senior CPU Verification Engineer - RSU Eligible

Qualcomm; United States; On-site; USD 167,100 - 250,700; Full time

Benefits offered by this job

Annual bonus

RSU grants

Job summary

Qualcomm Technologies, Inc. is seeking a Design Verification Engineer to validate CPU and SOC micro-architectures. You will work with Chip Architects to ensure launch-ready verification of key components.

You will develop verification plans, environments, and testbenches, and lead DV activities, reporting progress with metrics and debugging test failures to ensure reliability at product launch.

Qualifications

• BS/MS/PhD in EE/CE/CS with related work experience.
• 4+ years hardware/software engineering or related field for BS.
• 3+ years for MS; 2+ years for PhD.

Responsibilities

• Collaborate with CPU and SOC Architects to understand system requirements.
• Develop detailed Test and Coverage plans from architecture.
• Create Verification methodology scalable across environments.
• Build verification environment with stimulus, checkers, assertions, trackers, coverage.
• Develop testbenches and plans for functional domains.
• Execute plans, bring up DV environment, run regressions, debug failures.
• Track DV progress using metrics like bugs and coverage.

Skills

RISC-V

CPU/SoC verification

Testbenches

Formal methods

Silicon bringup

Test plans

leadership

Education

Bachelor's in Electrical Engineering / Computer Engineering / Computer Science

MS in Electrical Engineering / Computer Engineering / Computer Science

PhD in Electrical Engineering / Computer Engineering / Computer Science

Tools

Simulators

Gate-level Simulation

Waveform viewers

Coverage tools

Transactors

Job description

Qualcomm Technologies, Inc. is seeking a Design Verification Engineer to validate CPU and SOC micro-architectures. You will work with Chip Architects to ensure launch-ready verification of key components.

You will develop verification plans, environments, and testbenches, and lead DV activities, reporting progress with metrics and debugging test failures to ensure reliability at product launch.