Memory Subsystem Architect & P&R Engineer

Broadcom Inc.; Mendota Heights (MN); Hybrid; USD 110,000 - 176,000; Full time

Job summary

Broadcom Inc. in Mendota Heights is seeking a Memory System Designer and Place & Route Engineer to contribute to memory subsystem design, architecture, and RTL implementations. The role requires hands-on RTL, place & route, and design-closure expertise in a fast-paced environment.

The candidate should have 8+ years of relevant experience, strong Verilog and Python skills, and experience with STA/DRC/EMIR tools to ensure high-quality design closures and robust memory blocks.

Qualifications

• Minimum 8 years of relevant experience in memory subsystem design.
• Bachelor's degree in Electrical Engineering required.
• Strong RTL design and debugging skills; place & route and design closure experience required.

Responsibilities

• Architect and design memory subsystems.
• Implement RTL of subsystem designs.
• Place and route (physical design).
• Design closure: timing, DRC, LVS, EM/IR, etc.
• Gate netlist synthesis.

Skills

Verilog RTL

Place & Route

STA/DRC/EMIR

Python scripting

Synthesis tools

Memory behavior

Automation scripts

Leadership

Communication

Multitasking

Education

Bachelor's degree in Electrical Engineering

Tools

Verilog

STA/DRC tools

Synthesis tools

Python

Job description

Broadcom Inc. in Mendota Heights is seeking a Memory System Designer and Place & Route Engineer to contribute to memory subsystem design, architecture, and RTL implementations. The role requires hands-on RTL, place & route, and design-closure expertise in a fast-paced environment.

The candidate should have 8+ years of relevant experience, strong Verilog and Python skills, and experience with STA/DRC/EMIR tools to ensure high-quality design closures and robust memory blocks.