Memory Subsystem Architect & Physical Design Lead

Broadcom Inc.; Austin (TX); On-site; USD 110,000 - 176,000; Full time

Benefits offered by this job

Medical, dental, vision plans

401(K) with company match

Employee Stock Purchase Program (ESPP)

Employee Assistance Program (EAP)

Paid holidays

Sick leave and vacation time

Job summary

Broadcom Inc. is seeking an experienced design engineer to join the Central Engineering Group for memory subsystem development. You will design memory blocks, implement RTL, and drive timing and physical design closure.

The role requires strong Verilog, RTL, place-and-route, and scripting skills, with leadership and collaboration across teams. Eligible for bonus and equity awards as part of compensation.

Qualifications

• Typically requires a minimum of 8 years of relevant experience and a Bachelor's in Electrical Engineering.
• Experience writing and debugging Verilog RTL code.
• Proven ability to design memory subsystems and optimize timing through closure.
• Familiarity with physical design flow and tooling.

Responsibilities

• Architect and design memory subsystems and blocks.
• Implement RTL of subsystem designs.
• Perform place and route (physical design).
• Lead design closure: timing, DRC, LVS, EM/IR.
• Conduct gate netlist synthesis.

Skills

Verilog RTL

Place & Route

Python

Synthesis Tools

STA/DRC/EM-IR

Memory Subsystems

Automation Scripting

Leadership Skills

Communication Skills

Education

Bachelor's degree in Electrical Engineering

Tools

STA/DRC/EM-IR tools

Place & Route tools

Synthesis tools

Job description

Broadcom Inc. is seeking an experienced design engineer to join the Central Engineering Group for memory subsystem development. You will design memory blocks, implement RTL, and drive timing and physical design closure.

The role requires strong Verilog, RTL, place-and-route, and scripting skills, with leadership and collaboration across teams. Eligible for bonus and equity awards as part of compensation.